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| doc. no. 1137, rev. 6 september 16, 1999 5 / & 6 0 9 d qg 5 / & 6 0 $ q \ 3 r u w 70 70 0 x o w l 6 h u y l f h $ ff h vv 3 u r f h vv r u + d u g z d u h , q w h u i d f h ' h v f u l s w l r q
rl56csmv/3 and rl56csm/3 hardware interface description ii conexant 1137 information provided by conexant systems, inc. is believed to be accurate and reliable. however, no responsibility is assumed b y conexant for its use, nor any infringement of patents, copyrights, or other rights of third parties which may result from its use. no li cense is granted by implication or otherwise under any patent rights or copyright of conexant other than for circuitry embodied in conexant product s. conexant reserves the right to change circuitry at any time without notice. this document is subject to change without notice. conexant products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a conexant product can reasonably be expected to result in personal injury or death. conexant customers using or selling conexant products for use in such applications do so at their own risk and agree to fully indemnify conexant for any damages resulting from such improper us e or sale. k56flex is a trademark of conexant systems, inc. and lucent technologies. conexant, the conexant c symbol, what's next in communications technologies, anyport, and mnp ec are trademarks of conexant systems, inc. arm is a trademark of arm ltd. product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of third parties [their respective companies]. all other marks mentioned herein are the property of their respective [holders] own ers. ?1999, conexant systems, inc. all rights reserved rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant iii table of contents 1. introduction................................................................................................................. ................................ 1-1 1.1 summary ..................................................................................................................... .......................... 1-1 1.2 features .................................................................................................................... .......................... 1-2 1.3 technical overview.......................................................................................................... ............... 1-3 1.3.1 general description ....................................................................................................... .............. 1-3 1.3.2 digital data pump (ddp) ................................................................................................... .......... 1-3 1.3.3 arm microcontroller (mcu)................................................................................................. ........ 1-3 1.3.4 access processor operation ................................................................................................ ....... 1-3 1.3.5 access processor firmware ................................................................................................. ....... 1-3 1.3.6 supported interfaces ...................................................................................................... ............. 1-5 2. technical specifications ..................................................................................................... ................... 2-1 2.1 establishing data modem connections................................................................................... 2-1 2.2 data mode ................................................................................................................... ......................... 2-1 2.3 error correction and data compression............................................................................. 2-2 2.4 fax operation ............................................................................................................... ..................... 2-2 2.5 diagnostics................................................................................................................. ........................ 2-2 2.5.1 commanded tests........................................................................................................... ............ 2-2 2.5.2 ddp test .................................................................................................................. ................... 2-3 2.6 low power sleep mode........................................................................................................ ........... 2-3 3. hardware interface ........................................................................................................... ...................... 3-1 3.1 hardware signals ............................................................................................................ ................ 3-1 3.2 electrical and environmental specifications .................................................................. 3-15 3.2.1 operating conditions and absolute maximum ratings ............................................................. 3-15 3.2.2 current and power requirements ............................................................................................ .3-15 3.2.3 thermal characteristics................................................................................................... .......... 3-17 3.3 interface timing and waveforms............................................................................................. 3 -19 3.3.1 external sdram............................................................................................................ ............ 3-19 3.3.2 t1/e1 transceiver interface timing........................................................................................ ... 3-20 3.3.3 oscillator waveform requirements .......................................................................................... .3-21 3.4 sdram interface connections ................................................................................................. .3-22 3.4.1 16-mbit sdram interface ................................................................................................... ....... 3-22 3.4.2 64-mbit sdram interface ................................................................................................... ....... 3-23 4. host interface............................................................................................................... .............................. 4-1 4.1 registers and fifo .......................................................................................................... ................. 4-1 4.2 host interface description.................................................................................................. ....... 4-3 4.2.1 mailbox interface ......................................................................................................... ................ 4-4 4.2.2 host fifo interface ....................................................................................................... .............. 4-4 4.2.3 host bus timing ........................................................................................................... ............... 4-7 4.2.4 host interface - dma demand mode timing ............................................................................... 4-9 4.2.5 host interface pin summary ................................................................................................ ...... 4-11 5. design considerations ........................................................................................................ ..................... 5-1 5.1 pc board layout guidelines.................................................................................................. ....... 5-1 5.1.1 general principles ........................................................................................................ ............... 5-1 5.1.2 component placement ....................................................................................................... ......... 5-1 5.1.3 signal routing ............................................................................................................ ................. 5-1 5.1.4 power..................................................................................................................... ...................... 5-2 5.1.5 ground planes............................................................................................................. ................ 5-2 5.1.6 clock oscillator circuit.................................................................................................. ............... 5-2 5.1.7 emi considerations for standalone modem design .................................................................... 5-3 5.1.8 optional configurations ................................................................................................... ............ 5-3 5.1.9 ddp specific.............................................................................................................. .................. 5-3 rl56csmv/3 and rl56csm/3 hardware interface description iv conexant 1137 5.2 oscillator specifications ................................................................................................... ......... 5-4 5.3 package dimensions.......................................................................................................... ............... 5-6 5.4 plastic bga handling and use................................................................................................ ...... 5-8 5.4.1 handling.................................................................................................................. ..................... 5-8 5.4.2 circuit card design....................................................................................................... ............... 5-8 5.4.3 solder reflowing.......................................................................................................... ................ 5-8 5.4.4 inspection ................................................................................................................ .................... 5-9 5.4.5 rework and removal........................................................................................................ ........... 5-9 5.4.6 moisture .................................................................................................................. ..................... 5-9 5.4.7 references ................................................................................................................ .................. 5-9 rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant v list of figures figure 1-1. system implementation example block diagram ........................................................................ .......................... 1-4 figure 3-1. rl56csmv/3 hardware interface signals .............................................................................. ............................... 3-2 figure 3-2. rl56csmv/3 340-pin bga package ..................................................................................... ............................... 3-3 figure 3-3. multi die ball grid array package.................................................................................. ...................................... 3-17 figure 3-4. package internal heat removal path ................................................................................. ................................. 3-17 figure 3-5. connecting bga thermal balls to motherboard ground plane by using thermal vias..................................... .3-17 figure 3-6. test performance structure ......................................................................................... ........................................ 3-18 figure 3-7. sdram interface timing ............................................................................................. ........................................ 3-19 figure 3-8. tdm bus timing diagram............................................................................................. ....................................... 3-20 figure 3-9. oscillator waveform requirements ................................................................................... .................................. 3-21 figure 3-10. 16-mbit sdram interface connections ............................................................................... .............................. 3-22 figure 3-11. 64-mbit sdram interface connections ............................................................................... .............................. 3-23 figure 4-1. host interface block diagram ....................................................................................... ......................................... 4-1 figure 4-2. reference direction for modem data ................................................................................. .................................. 4-3 figure 4-3. waveforms - host read.............................................................................................. ........................................... 4-7 figure 4-4. waveforms - host write ............................................................................................. ............................................ 4-8 figure 4-5. host dma demand mode read, dmamode = 1 ............................................................................. ..................... 4-9 figure 4-6. host dma demand mode write, dmamode = 1 ............................................................................ .................... 4-10 figure 5-1. package dimensions - 340-pin bga ................................................................................... .................................. 5-7 figure 5-2. plated hole placement guideline for connection to bga ball ......................................................... ..................... 5-8 list of tables table 1-1. rl56csmv/3 and rl56csm/3 models and functions....................................................................... .................... 1-1 table 1-2. logical channel vs. physical channel ................................................................................ .................................... 1-4 table 1-3. typical sdrams ...................................................................................................... ............................................... 1-5 table 3-1. rl56csmv/3 pin signals by pin location.............................................................................. ................................ 3-4 table 3-2. rl56csmv/3 pin signals by interface................................................................................. ................................... 3-6 table 3-3. rl56csmv/3 signal definitions....................................................................................... ....................................... 3-8 table 3-4. i/o type descriptions............................................................................................... ............................................. 3-13 table 3-5. digital electrical characteristics.................................................................................. .......................................... 3-14 table 3-6. operating conditions................................................................................................ ............................................. 3-15 table 3-7. absolute maximum ratings............................................................................................ ....................................... 3-15 table 3-8. current and power requirements...................................................................................... ................................... 3-16 table 3-9. thermal characteristics ............................................................................................. ........................................... 3-16 table 3-10. sdram interface timing............................................................................................. ........................................ 3-19 table 3-11. timing C t1/e1 transceiver ......................................................................................... ....................................... 3-20 table 4-1. host control, status and i/o registers .............................................................................. ..................................... 4-2 table 4-2. timing - host read .................................................................................................. ............................................... 4-7 table 4-3. timing - host write................................................................................................. ................................................. 4-8 table 4-4. host bus interface pin description.................................................................................. ...................................... 4-11 table 5-1. clock oscillator specifications - surface mount..................................................................... ................................. 5-4 table 5-2. clock oscillator specifications - through hole ...................................................................... ................................. 5-5 rl56csmv/3 and rl56csm/3 hardware interface description vi conexant 1137 document revision record changes incorporated in revision 6 1. figure 1-1: revised sdram box. 2. table 1-3: added sdram part numbers. 3. figure 1-1: revised sdram box. 4. table 3-3: revised x_sclk i/o type. 5. table 3-4: added itpu/ot2 i/o type. 6. table 3-5: revised output voltage low and output voltage high test conditions. 7. section 3.4: added. changes incorporated in revision 5 8. throughout: replaced vcc with vdd. 9. throughout: replaced vgg5v with vgg. 10. figure 1-1: corrected x_sclk label. 11. figure 3-1: corrected rw# label and added clk label. 12. section 3.2: added section headings and reorganized. 13. table 3-1: corrected rw# label. 14. table 3-2: corrected rw# label. 15. table 3-3: corrected mcu_test# i/o type to itpu and corrected rw# label. 16. table 3-4: updated c in from 7 pf to 8pf. 17. table 3-5: added new table. 18. table 3-8: added power requirements for rl56csmv/3. 19. section 3.2.3: revised thermal characteristics. 20. section 3.3: replaced table 3-10 and figure 3-3. 21. table 3-11: added notes. 22. table 4-2: added notes. 23. table 3-3: added notes. 24. table 3-6: revised. 25. table 3-9: replaced vdd in limits with vgg, revised maximum supply voltage to 4.0 v, added latch-up current @ 125 c. 26. table 3-10: revised. 27. figure 3-3: revised. 28. section 3.2.3: revised notes. 29. table 4-2: corrected t cs symbol. 30. figure 4-3: revised. 31. figure 4-4: revised. 32. table 5-1: revised. 33. table 5-2: revised. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant vii changes incorporated in revision 4 1. added rl56csmv/3 voice enabled part to the anyport family. 2. added table 3-10, sdram interface timing and figure 3-3. sdram interface timing 3. added figure 3-5, oscillator waveform requirements. 4. updated and corrected figure 3-1, rl56csmv/3 hardware interface signals. 5. renamed channel signal names to match logical channels, as follows: old "a_name" changed to "c_name", old "b_name" changed to "a_name", old "c_name" changed to "b_name". note: this is a signal name change only. there is no functional change to device operation. %doo 2og 1dph 1hz 1dph %doo 2og 1dph 1hz 1dph %doo 2og 1dph 1hz 1dph $& $b6&/. &b6&/. * %b6&/. $b6&/. ) &b6&/. %b6&/. $% $b)6<1& &b)6<1& + %b)6<1& $b)6<1& ( &b)6<1& %b)6<1& $' $b5;'$7$ &b5;'$7$ . %b5;'$7$ $b5;'$7$ & &b5;'$7$ %b5;'$7$ $& $b7;'$7$ &b7;'$7$ / %b7;'$7$ $b7;'$7$ % &b7;'$7$ %b7;'$7$ 9 $b3//9'' &b3//9'' & %b3//9'' $b3//9'' * &b3//9'' %b3//9'' $' $b3//*1' &b3//*1' 1 %b3//*1' $b3//*1' & &b3//*1' %b3//*1' 3 $b(<(;< &b(<(;< $ %b(<(;< $b(<(;< / &b(<(;< %b(<(;< $$ $b(<(6<1& &b(<(6<1& ) %b(<(6<1& $b(<(6<1& * &b(<(6<1& %b(<(6<1& < $b(<(&/. &b(<(&/. ( %b(<(&/. $b(<(&/. + &b(<(&/. %b(<(&/. 8 $b76$(1 &b76$(1 $ %b76$(1 $b76$(1 - &b76$(1 %b76$(1 5 $b;&/. &b;&/. $ %b;&/. $b;&/. & &b;&/. %b;&/. 5 $b<&/. &b<&/. $ %b<&/. $b<&/. & &b<&/. %b<&/. 6. updated table 1-2, logical channel vs. physical channel. 7. added table 3-4, i/o type descriptions. 8. updated table 3-5, digital electrical characteristics. 9. updated section 5.1.6, clock oscillator circuit. rl56csmv/3 and rl56csm/3 hardware interface description viii conexant 1137 this page is intentionally blank. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 1-1 1. introduction 1.1 summary the rl56csmv/3 and rl56csm/3 are members of the conexant ? anyport? family of multi-service access processors, and provide a complete solution to the transport of multiple media types between circuit-switched remote access and a variety of back-end networks. anyport processors are ideally suited for the network infrastructures resulting from the convergence of voice and data networking, addressing new requirements such as voice and fax over packet networks, isdn and cellular data, while maintaining support of traditional pstn data/fax needs. note: in this document, rl56csmv/3 and csmv/3 refer to both rl56csmv/3 and rl56csm/3 except as noted. any reference to voice applies only to the rl56csmv/3. the csmv/3 transcends existing modem solutions by providing a complete system solution for multi-service remote access. the combined dsp/risc architecture provides an ideal engine to run conexants extensive suite of field-proven modulations, echo cancellers, voice coders, and communications protocols. in addition, performing functions such as t.38, v.120, async to sync hdlc conversion for ppp, v.110, and synchronous hdlc for ppp on isdn connections, in the access processor allows system designers to reduce system overhead and increase scalability. the csmv/3 is a low-power system providing three communication channels in a single package. powerful and downloadable dsp-based data pumps employ on-chip sram to allow upgrades to future voice and communication modulation schemes. an advanced risc microcontroller manages three data pumps simultaneously. an innovative host interface to the multi-service access processor system uses a shared sdram memory to increase data throughput while reducing system cost and space. a programmable time slot selection feature provides direct digital connection to a t1/e1/pri framing device. a 35mm bga package houses the csmv/3 with extra balls available for thermal vias to minimize heat. a built-in phase lock loop (pll) minimizes board noise while easing design. a quick-wake, sleep mode further reduces the power of this +3.3v access processor system. this hardware interface description describes the modem hardware capabilities. at commands and s registers are defined in the at command reference manual (order no. 1195). additional information is described in the software interface description (order no. 1148) and the rl56ddp modem designers guide (order no. 1141). table 1-1. rl56csmv/3 and rl56csm/3 models and functions 0rgho2ughu3duw 1xpehuv 6xssruwhg )xqfwlrqv 0dunhwlqj 0rgho 1xpehu 3duw 1xpehu 3lq %*$ 'dwd )d[ 9rlfh 5/&60 5 rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 1-3 1.3 technical overview 1.3.1 general description the csmv/3 provides the processing core for three channels of a central site remote access server supporting high speed t1/e1/pri digital lines. the oem adds two oscillators, sdram, and discrete components to complete the multi-service access processor system. the access processor includes a full-featured, self-contained data/fax/voice modem solution shown in figure 1-1. data modem handshake, fax modem protocol, voice codecs, and isdn data connection functions are supported and controlled through the at command set. 1.3.2 digital data pump (ddp) the ddp is a +3.3v conexant data pump supporting pstn data/fax modem operation, isdn b channel call termination mode, and voice coding/decoding. the ddp executes internal code including downloadable modules from on-chip memory. digital data transfers serially between the t1/e1 framer device and the ddp at a data rate up to 8.192 mbps. the t1/e1 framing device provides a strobe signal and the ddp tsa logic detects where the data for the channel starts in the serial tdm data stream using a programmable counter. the ddp performs pcm -law or a-law conversion and synchronizes with an external network clock. 1.3.3 arm microcontroller (mcu) the arm mcu performs the command processing and interfaces to the central site system controller via a 16-bit parallel host interface. two 64-word deep fifos are used for improved data throughput between the access processor and system controller. this single powerful risc processor controls three separate channels. a sdram loader is available to support download from the central site system controller on startup, if desired. 1.3.4 access processor operation in data modem modes, each channel can independently connect to pstn data modems at rates up to 56 kbps or isdn terminal adapters at rates up to 64 kbps. a downloadable architecture allows for software download. for pstn modems, complete handshake and data rate negotiations are performed. by optimizing the modem configuration for line conditions, the ddp can connect at the highest data rate that the channel can support from 56 kbps to 300 bps with automatic fallback. automode operation in v.34 is provided in accordance with pn3320 and in v.32 bis in accordance with pn2330. all tone and pattern detection functions required by the applicable itu or bell standard are supported. asynchronous to synchronous conversion is supported inside the controller to ease ppp processing in pstn data mode. when the remote end is an isdn terminal adapter, the csmv/3 provides hdlc control including hdlc flag generation/detection, bit stuffing/extraction, and crc generation/checking. v.120, v.110, and lap-b x.75 are also supported. v.120 is a standard for encapsulating asynchronous data communications traffic into isdn data streams. in fax modem mode, the csmv/3 supports group 3 facsimile send and receive speeds of 14400, 12000, 9600, 7200, 4800, and 2400 bps. fax modem modes support t.30 fax requirements. fax data transmission and reception performed by the access processor are controlled and monitored through the eia-578 class 1 and class 2 command interface. both transmit and receive fax data are buffered within the access processor. in voice mode, the csmv/3 encodes pcm audio data from the line into real-time protocol (rtp) packets for the host, and decodes rtp packets from the host, to output pcm audio data to the line. in voice mode, dtmf digits can be detected and transmitted, and a voice activity detector can be enabled. 1.3.5 access processor firmware access processor firmware performs processing of general modem control, command sets, error correction and data compression, fax class 1 and class 2, voice coding and decoding (optional), and central site system controller interface functions. the firmware is provided in object code form for executing from external sdram after download on startup using the rom- coded boot loader. equipment designers can add their own functions in firmware using commonly available development tools and the c programming language. rl56csmv/3 and rl56csm/3 hardware interface description 1-4 conexant 1137 md233f1 csmv/3 if mcu_clkin +5v +3.3v gnd power supply a_sclk a_fsync a_rxdata a_txdata a_tsaen# rl56csmv/3 ch b address (5) data (16) control status memory bus ( mb ) ch a customer system controller rl56ddp digital data pump (ddp) b_sclk b_fsync b_rxdata b_txdata b_tsaen# rl56ddp digital data pump (ddp) micro controller unit (mcu) mcu clock t1/e1 or primary rate line interface t1/e1 transceiver/ framer conexant bt8370 or equivalent) sclk fsync rxdata txdata ch c c_sclk c_fsync c_rxdata c_txdata c_tsaen# rl56ddp digital data pump (ddp) host bus ( hb ) dp_clkin ddp clock vgg vdd gnd 16 mbit (2 x 512 k x 16) or 64 mbit (4 x 1 m x 16) sdram figure 1-1. system implementation example block diagram note: table 1-2 shows the ddp (physical) channel corresponding to the logical channel number programmed in the mailbox messages. the logical channel corresponds to the physical channel as follows: 0 = a, 1 = b, and 2 = c. table 1-2. logical channel vs. physical channel logical channel corresponding physical channel logical channel 0 physical channel a logical channel 1 physical channel b logical channel 2 physical channel c rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 1-5 1.3.6 supported interfaces parallel host bus interface the interface signals are: 16 bidirectional data lines (hbd0-hbd15), five address input lines (hba1-hba5), and six control lines (hbcs#, hbrd#, hbwr#, hben#, hbackr#, and hbackw#). refer to the software interface description (order no. 1148) for fifo and mailbox description. t1/e1 transceiver interface the 4-line interface to the oem-supplied t1/e1 transceiver consists of the sclk, fsync, and rxdata inputs and the txdata output. the t1/e1 transceiver interface timing is described in section 3.2.3. sdram interface the csmv/3 provides address, data, and control lines to connect to a 16 mbit (2 x 512 k x 16) or 64 mbit (4 x 1 m x 16) synchronous dynamic ram (sdram) meeting the intel pc100 specification. typical sdrams that meet csmv/3 requirements are listed in table 1-3. table 1-3. typical sdrams manufacturer part number 16-mbit sdrams nec upd4516161ag5-a80 upd4516161ag5-a10 upd4516161ag5-a10b hyundai hy57v161610ctc-8 hy57v161610ctc-10p hy57v161610ctc-10s fujitsu mb81f161622b -60 mb81f161622b-70 mb81f161622b-80 micron mt48lc1m16a1-tg-7se 64-mbit sdrams nec upd4564163g5-a10-9jf mitsubishi m2v64s40btp rl56csmv/3 and rl56csm/3 hardware interface description 1-6 conexant 1137 this page is intentionally blank. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 2-1 2. technical specifications 2.1 establishing data modem connections in a typical application, the system controller processes all aspects of pstn connection call setup, including off-hook signaling, sending dial digits, call progress detection, and ring detection for both t1/e1 lines and isdn d-channel control. after a pstn connection is established by the system controller, the system controller issues the ata command to the csmv/3 to start the answer handshake sequence, or the atd command to start the originate handshake sequence. modem handshaking protocol if a handshake is not completed within the time specified in the s7 register after the atd or ata command is issued, the modem aborts the handshake attempt. answer tone detection answer tone can be detected over the frequency range of 2100 40 hz in itu-t modes and 2225 40 hz in bell modes. billing protection when the modem goes off-hook to answer an incoming call, both transmission and reception of data are prevented for 2 seconds (data modem) or 4 seconds (fax adaptive answer) to comply with the billing delay requirement. connection speeds and codec selection the modem functions as a data modem when the +fclass=0 command is active. line connection can be selected using the +ms command in accordance with the draft pn-3320 standard presented to the tr30-4 committee (which is a candidate for the definition of v.25 ter at the itu). the +ms command selects modulation, enables/disables automode, selects minimum and maximum line speeds, and selects m -law or a-law codec. the +ms command is described in the at command reference manual (order no. 1195). multi-frequency (mf) tone generation and detection multi-frequency (mf) tone generation and detection is supported by the +vts, +ctd, +ptf, and +qtr commands. the +vts, +ctd, +ptf, and +qtr commands are described in the at command reference manual (order no. 1195). 2.2 data mode data mode exists when a connection has been established between modems and all handshaking has been completed. speed buffering (normal mode) speed buffering allows a dte to send data to, and receive data from, a modem at a speed different than the line speed. the modem supports speed buffering at all line speeds. flow control dte-to-modem flow control. refer to the software interface description (order no. 1148). escape sequence detection the +++ escape sequence can be used to return control to the command mode from the data mode. escape sequence detection is disabled by an s2 register value greater than 127, (or use &d2 and dtr drop - see s25 register, at command reference manual, order no. 1195). refer to the software interface description (order no. 1148). break generation and detection refer to the software interface description (order no. 1148). telephone line monitoring gstn cleardown (v.90, k56flex, v.34, v.32 bis, v.32). upon receiving gstn cleardown from the remote modem in a non- error correcting mode, the modem cleanly terminates the call. rl56csmv/3 and rl56csm/3 hardware interface description 2-2 conexant 1137 fall forward/fallback (v.34/v.32 bis/v.32) during initial handshake, the modem will fallback to the optimal line connection within v.34/v.32 bis/v.32 mode depending upon signal quality if automode is enabled by the +ms or n1 command. when connected in v.34/v.32 bis/v.32 mode, the modem will fall forward or fallback to the optimal line speed within the current modulation depending upon signal quality if fall forward/fallback is enabled by the %e2 command. retrain the modem may lose synchronization with the received line signal under poor line conditions. if this occurs, retraining may be initiated to attempt recovery depending on the type of connection. the modem initiates a retrain if line quality becomes unacceptable if enabled by the %e command. the modem continues to retrain until an acceptable connection is achieved, or until 30 seconds elapse resulting in line disconnect. programmable inactivity timer the modem disconnects from the line if data is not sent or received for a specified length of time. in normal or error-correcti on mode, this inactivity timer is reset when data is received from either the dte or from the line. this timer can be set to a val ue between 0 and 2550 seconds by using register s30. a value of 0 disables the inactivity timer. 2.3 error correction and data compression v.42 error correction v.42 supports two methods of error correction: lapm and, as a fallback, mnp 4. the modem provides a detection and negotiation technique for determining and establishing the best method of error correction between two modems. mnp 2-4 error correction mnp 2-4 is a data link protocol that uses error correction algorithms to ensure data integrity. supporting stream mode, the modem sends data frames in varying lengths depending on the amount of time between characters coming from the dte. v.42 bis data compression v.42 bis data compression mode, enabled by the %cn command or s46 register, operates when a lapm or mnp 10ec connection is established. the v.42 bis data compression employs a string learning algorithm in which a string of characters from the dte is encoded as a fixed length codeword. two 2k-byte dictionaries are used to store the strings. these dictionaries are dynamically updated during normal operation. mnp 5 data compression mnp 5 data compression mode, enabled by the %cn command, operates during an mnp connection. in mnp 5, the modem increases its throughput by compressing data into tokens before transmitting it to the remote modem, and by decompressing encoded received data before sending it to the dte. 2.4 fax operation facsimile functions operate in response to fax class 1 commands when +fclass=1 or in response to fax class 2 commands when +fclass=2. in the fax mode, the on-line behavior of the modem is different from the data (non-fax) mode. after dialing, modem operation is controlled by fax commands. other at commands are still valid but may operate differently than in data modem mode. calling tone is generated in accordance with t.30. 2.5 diagnostics 2.5.1 commanded tests diagnostics are performed in response to &t commands, per v.54. remote digital loopback (rdl) (&t6 command). data from the local dte is sent to the remote modem which loops the data back to the local dte. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 2-3 remote digital loopback with self test (&t7 command). an internally generated pattern is sent from the local modem to the remote modem, which loops the data back to the local modem. local digital loopback (&t3 command). when local digital loop is requested by the local dte, two data paths are set up in the local modem. data from the local dte is looped back to the local dte (path 1) and data received from the remote modem is looped back to the remote modem (path 2). 2.5.2 ddp test following an sdram download, the rom-coded boot loader jumps to the starting address of the mcu firmware, and the mcu firmware will try to configure the ddps. if any ddp does not configure correctly, that channel is reported as "down", and at commands that require access to the ddp (e.g., atd, ata, ath, or atz) will respond with error. 2.6 low power sleep mode sleep mode entry. the ddps enter the low power sleep mode when no line connection exists and no datapump activity occurs for the period of time specified in the s24 register. all ddp circuits are turned off in order to consume reduced power while being able to immediately wake up and resume normal operation. wake-up. when the host requests a channel to be active, the mcu will wake-up the datapump for that channel. the wake-up process is transparent to the host. rl56csmv/3 and rl56csm/3 hardware interface description 2-4 conexant 1137 this page is intentionally blank. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-1 3. hardware interface 3.1 hardware signals the rl56csmv/3 interface is illustrated in figure 3-1. the rl56csmv/3 bga pin (ball) locations are shown in figure 3-2. the rl56csmv/3 pin signals by pin location are listed in table 3-1. the rl56csmv/3 pin signals by interface are listed in table 3-2. the rl56csmv/3 hardware interface signals are defined in table 3-3. hardware interface signal i/o types are described in table 3-4. digital electrical characteristics for the hardware interface signals are listed in table 3-5. rl56csmv/3 and rl56csm/3 hardware interface description 3-2 conexant 1137 1137f3-1 csm/3 hwif a[12:1] d[15:0] mcu_clkout rw# ras# cas# bs0 bs1 power supply rl56csmv/3 mcu_clkin dp_clkin mcu_reset# rome mcu_test# dp_test# xycnt hba[5:1] hbd[15:0] hbclk hben# hbcs# hbrd# hbwr# hbackr# hbackw# hbrqstr hbrqstw hbirq# memory bus (mb) customer system controller host interface micro controller unit ( mcu ) dp clock t1/e1 or primary rate line interface t1/e1 transceiver/ framer conexant bt8370 or equivalent) sclk fsync rxdata txdata rl56ddp digital data pump ( ddp ) host bus (hb) mcu clock vdd vgg gnd rl56ddp digital data pump ( ddp ) a_pllvdd b_pllvdd c_pllvdd a_pllgnd b_pllgnd c_pllgnd rl56ddp digital data pump ( ddp ) jtag +3.3v +5v gnd wr# rd# cs1 a[11:0] d[15:0] clk we# ras# cas# dqml dqmu cs# nc nc nc 0.1 10 tant vdd + 10 ch a a_sclk a_fsync a_rxdata a_txdata a_tsaen# a_dprst# a_pllvdd a_pllgnd 20k 33 ch b b_sclk b_fsync b_rxdata b_txdata b_tsaen# b_dprst# b_pllvdd b_pllgnd 20k 33 ch c c_sclk c_fsync c_rxdata c_txdata c_tsaen# c_dprst# 20k 33 tck tdi tdo tms trst# dpbs_tclk dpbs_tdi dpbs_tdo dpbs_tms dpbs_trst# 3k 3k 16 mbit (2 x 512 k x 16) sdram* * connection to 64 mbit ( 4 x 1 m x 16 ) sdram also supported. see hardware interface description, section 3.4, for detail interface connection. figure 3-1. rl56csmv/3 hardware interface signals rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-3 pin a1 corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af top view bottom view md194f4 268bga figure 3-2. rl56csmv/3 340-pin bga package rl56csmv/3 and rl56csm/3 hardware interface description 3-4 conexant 1137 table 3-1. rl56csmv/3 pin signals by pin location 7deoh &ro 7deoh 5rz /rf 6ljqdo ,) /rf 6ljqdo ,) /rf 6ljqdo ,) /rf 6ljqdo ,) $ &b'3567 *1' wkux . % %b'35;&/. 7(67 ) 9'' 9 . $b'37;&/. 7(67 $ $b'3567 *1' wkux . % 5(6(59(' ) 5(6(59(' . $b5;'$7$ &+ $ $ %b'3567 *1' wkux . & %b5;'$7$ &+ % ) *1' *1' / ' 0% $ 9** 9 & 5(6(59(' ) *1' *1' / ' 0% $ %b'3&6 7(67 & 5(6(59(' ) *1' *1' / %b(<(;< &+ % $ $ 0% & 5(6(59(' ) *1' *1' / ;<&17 7(67 $ $ 0% & 9'' 9 ) *1' *1' / 5(6(59(' $ $ 0% & %b<&/. &+ % ) *1' *1' / $b7;'$7$ &+ $ $ $ 0% & %b;&/. &+ % ) 5(6(59(' 0 ' 0% $ $ 0% & %b'63567 7(67 ) '3b7(67 7(67 0 ' 0% $ ' 0% & %b3//*1' &+ % ) 5(6(59(' 0 ' 0% $ ' 0% & 5(6(59(' ) $b(<(6<1& &+ $ 0 9'' 9 $ ' 0% & '3%6b7567 -7$* * %b(<(6<1& &+ % 0 $b'3&6 7(67 $ ' 0% & 9'' 9 * 5(6(59(' 0 $b'63567 7(67 $ '3b&/.,1 6<6 & %b'3,17 7(67 * %b3//9'' &+ % 1 ' 0% $ 5(6(59(' & 5(6(59(' * 5(6(59(' 1 ' 0% $ $b'3,17 7(67 & 9'' 9 * *1' *1' 1 ' 0% $ $b'63,17 7(67 & $b3//9'' &+ $ * *1' *1' 1 :5 0% $ $b(<(;< &+ $ & 5(6(59(' * *1' *1' 1 $b3//*1' &+ $ $ $b;&/. &+ $ & 5(6(59(' * *1' *1' 1 '3%6b7&/. -7$* $ $b<&/. &+ $ & 5(6(59(' * *1' *1' 3 &$6 0% $ 5(6(59(' & 5(6(59(' * *1' *1' 3 5$6 0% $ $b76$(1 &+ $ & 5(6(59(' * 5(6(59(' 3 0&8b&/.,1 6<6 $ 5(6(59(' & 5(6(59(' * 5(6(59(' 3 &b'63,17 7(67 $ 5(6(59(' & $b'37;' 7(67 * 5(6(59(' 3 5' 0% $ 5(6(59(' & 9'' 9 * $b6&/. &+ $ 3 &b(<(;< &+ & % %b7;'$7$ &+ % & 5(6(59(' + %b(<(&/. &+ % 5 3$ 1$ % 5(6(59(' & 5(6(59(' + 5(6(59(' 5 5(6(59(' % 5(6(59(' ' 5(6(59(' + %b'63,17 7(67 5 0&8b&/.287 0% % 5(6(59(' ' 5(6(59(' + 5(6(59(' 5 &b'37;&/. 7(67 % 5(6(59(' ' 5(6(59(' + *1' *1' 5 &b<&/. &+ & % 5(6(59(' ' 9'' 9 + *1' *1' 5 &b;&/. &+ & % &b'3(;567 7(67 ' $ 0% + *1' *1' 7 3$ 1$ % $b'3(;567 7(67 ' 5(6(59(' + *1' *1' 7 3( 1$ % %b'3(;567 7(67 ( %b)6<1& &+ % + *1' *1' 7 9'' 9 % ' 0% ( 5(6(59(' + *1' *1' 7 &b'3,17 7(67 % ' 0% ( 5(6(59(' + 5(6(59(' 7 9'' 9 % ' 0% ( 5(6(59(' + 9'' 9 7 9'' 9 % ' 0% ( 5(6(59(' + 5(6(59(' 8 3$ 1$ % &b'35;' 7(67 ( 5(6(59(' + $b)6<1& &+ $ 8 3( 1$ % 5(6(59(' ( 5(6(59(' - 5(6(59(' 8 9'' 9 % 5(6(59(' ( 5(6(59(' - %b76$(1 &+ % 8 9** 9 % 5(6(59(' ( 5(6(59(' - 9'' 9 8 &b76$(1 &+ & % $b'35;' 7(67 ( 5(6(59(' - 5(6(59(' 8 5(6(59(' % 5(6(59(' ( 5(6(59(' - 5(6(59(' 9 3( 1$ % 5(6(59(' ( 5(6(59(' - 5(6(59(' 9 3( 1$ % 5(6(59(' ( 5(6(59(' . %6 0% 9 5(6(59(' % %b'35;' 7(67 ( $b(<(&/. &+ $ . '3%6b7'2 -7$* 9 &b'35;&/. 7(67 % %b'37;' 7(67 ) %b6&/. &+ % . 9'' 9 9 &b'37;' 7(67 % %b'37;&/. 7(67 ) 5(6(59(' . $b'35;&/. 7(67 9 &b3//9'' &+ & 1rwhv 5(6(59(' 0d\ kdyh lqwhuqdo flufxlw frqqhfwhg qr h[whuqdo frqqhfwlrq doorzhg rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-5 table 3-1. rl56csmv/3 pin signals by pin location (contd) 7deoh &ro 7deoh 5rz /rf 6ljqdo ,) /rf 6ljqdo ,) /rf 6ljqdo ,) /rf 6ljqdo ,) : 3$ 1$ $% 5(6(59(' $( +%$ +% : 3$ 1$ $% 5(6(59(' $( +%&6 +% : 9'' 9 $% 5(6(59(' $( +%:5 +% : *1' *1' $% 5(6(59(' $( +%&/. +% : *1' *1' $% &b)6<1& &+ & $( +%(1 +% : *1' *1' $% &6 0% $( $ 0% : *1' *1' $& 7567 -7$* $( $ 0% : *1' *1' $& 3) 1$ $( $ 0% : *1' *1' $& 9'' 9 $( $ 0% : *1' *1' $& &6 0% $( 9'' 9 : 5(6(59(' $& &b7;'$7$ &+ & $( 5(6(59(' : 0&8b5(6(7 6<6 $& &b6&/. &+ & $( $ 0% : 520( 6<6 $' 3) 1$ $( $ 0% : %6 0% $' 706 -7$* $( $ 0% < 3( 1$ $' 9'' 9 $) 3) 1$ < 3( 1$ $' 9'' 9 $) 3) 1$ < 9'' 9 $' 9'' 9 $) 7', -7$* < *1' *1' $' 9'' 9 $) +%$&.5 +% < *1' *1' $' 9'' 9 $) +%$&.: +% < *1' *1' $' 9'' 9 $) +%' +% < *1' *1' $' 9'' 9 $) +%' +% < *1' *1' $' 9'' 9 $) +%' +% < *1' *1' $' 9'' 9 $) +%' +% < *1' *1' $' +%' +% $) +%' +% < 5(6(59(' $' +%$ +% $) +%' +% < &b(<(&/. &+ & $' +%$ +% $) +%' +% < 0&8b7(67 6<6 $' '3%6b7', -7$* $) +%' +% < &6 0% $' &b3//*1' &+ & $) +%$ +% $$ 3( 1$ $' &b'63567 7(67 $) +%$ +% $$ 3( 1$ $' $ 0% $) +%5' +% $$ 9'' 9 $' &b'3&6 7(67 $) 5(6(59(' $$ *1' *1' $' $ 0% $) +%,54 +% $$ *1' *1' $' $ 0% $) $ 0% $$ *1' *1' $' $ 0% $) '3%6b706 -7$* $$ *1' *1' $' $ 0% $) $ 0% $$ *1' *1' $' 5: 0% $) $ 0% $$ *1' *1' $' &b5;'$7$ &+ & $) $ 0% $$ *1' *1' $' &6 0% $) $ 0% $$ 5(6(59(' $( 3) 1$ $) $ 0% $$ 9** 9 $( 7'2 -7$* $) $ 0% $$ &b(<(6<1& &+ & $( 7&. -7$* $$ &6 0% $( +%54675 +% $% 3) 1$ $( +%5467: +% $% 3) 1$ $( +%' +% $% 3) 1$ $( +%' +% $% *1' *1' $( +%' +% $% *1' *1' $( +%' +% $% *1' *1' $( +%' +% $% *1' *1' $( +%' +% $% 5(6(59(' $( +%' +% 1rwhv 5(6(59(' 0d\ kdyh lqwhuqdo flufxlw frqqhfwhg qr h[whuqdo frqqhfwlrq doorzhg rl56csmv/3 and rl56csm/3 hardware interface description 3-6 conexant 1137 table 3-2. rl56csmv/3 pin signals by interface 7deoh &ro 7deoh 5rz /rf 6ljqdo ,) /rf 6ljqdo ,) /rf 6ljqdo ,) /rf 6ljqdo ,) $( +%$ +% * %b(<(6<1& &+ % / ' 0% . $b'37;&/. 7(67 $' +%$ +% + %b(<(&/. &+ % / ' 0% & $b'37;' 7(67 $) +%$ +% - %b76$(1 &+ % 0 ' 0% $ $b'63,17 7(67 $) +%$ +% & %b;&/. &+ % 0 ' 0% 0 $b'63567 7(67 $' +%$ +% & %b<&/. &+ % 0 ' 0% $ %b'3&6 7(67 $) +%' +% $& &b6&/. &+ & 1 ' 0% % %b'3(;567 7(67 $( +%' +% $% &b)6<1& &+ & 1 ' 0% & %b'3,17 7(67 $) +%' +% $' &b5;'$7$ &+ & 1 ' 0% % %b'35;&/. 7(67 $) +%' +% $& &b7;'$7$ &+ & : %6 0% % %b'35;' 7(67 $( +%' +% 9 &b3//9'' &+ & . %6 0% % %b'37;&/. 7(67 $) +%' +% $' &b3//*1' &+ & $& &6 0% % %b'37;' 7(67 $( +%' +% 3 &b(<(;< &+ & $' &6 0% + %b'63,17 7(67 $( +%' +% $$ &b(<(6<1& &+ & $$ &6 0% & %b'63567 7(67 $) +%' +% < &b(<(&/. &+ & $% &6 0% ) '3b7(67 7(67 $( +%' +% 8 &b76$(1 &+ & < &6 0% / ;<&17 7(67 $) +%' +% 5 &b;&/. &+ & 3 5' 0% $ &b'3567 *1' wkux . $) +%' +% 5 &b<&/. &+ & $' 5: 0% $ $b'3567 *1' wkux . $( +%' +% $ $ 0% 1 :5 0% $ %b'3567 *1' wkux . $) +%' +% $ $ 0% 3 5$6 0% 7 3$ 1$ $' +%' +% $ $ 0% 3 &$6 0% : 3$ 1$ $( +%' +% $ $ 0% 5 0&8b&/.287 0% 5 3$ 1$ $( +%&/. +% $ $ 0% 3 0&8b&/.,1 6<6 : 3$ 1$ $( +%(1 +% $( $ 0% $ '3b&/.,1 6<6 8 3$ 1$ $( +%&6 +% $) $ 0% : 0&8b5(6(7 6<6 8 3( 1$ $) +%5' +% $( $ 0% : 520( 6<6 < 3( 1$ $( +%:5 +% $) $ 0% < 0&8b7(67 6<6 9 3( 1$ $) +%$&.5 +% $( $ 0% $( 7&. -7$* < 3( 1$ $) +%$&.: +% $) $ 0% $) 7', -7$* 7 3( 1$ $( +%54675 +% $' $ 0% $( 7'2 -7$* $$ 3( 1$ $( +%5467: +% $' $ 0% $' 706 -7$* 9 3( 1$ $) +%,54 +% $( $ 0% $& 7567 -7$* $$ 3( 1$ * $b6&/. &+ $ $( $ 0% 1 '3%6b7&/. -7$* $% 3) 1$ + $b)6<1& &+ $ $' $ 0% $' '3%6b7', -7$* $% 3) 1$ . $b5;'$7$ &+ $ $' $ 0% . '3%6b7'2 -7$* $% 3) 1$ / $b7;'$7$ &+ $ $) $ 0% $) '3%6b706 -7$* $& 3) 1$ & $b3//9'' &+ $ $) $ 0% & '3%6b7567 -7$* $) 3) 1$ 1 $b3//*1' &+ $ $) $ 0% $' &b'3&6 7(67 $( 3) 1$ $ $b(<(;< &+ $ $' $ 0% % &b'3(;567 7(67 $) 3) 1$ ) $b(<(6<1& &+ $ ' $ 0% 7 &b'3,17 7(67 $' 3) 1$ ( $b(<(&/. &+ $ $( $ 0% 9 &b'35;&/. 7(67 & 9'' 9 $ $b76$(1 &+ $ $) $ 0% % &b'35;' 7(67 & 9'' 9 $ $b;&/. &+ $ $( $ 0% 5 &b'37;&/. 7(67 & 9'' 9 $ $b<&/. &+ $ $ ' 0% 9 &b'37;' 7(67 & 9'' 9 ) %b6&/. &+ % % ' 0% 3 &b'63,17 7(67 ' 9'' 9 ( %b)6<1& &+ % % ' 0% $' &b'63567 7(67 ) 9'' 9 & %b5;'$7$ &+ % % ' 0% 0 $b'3&6 7(67 + 9'' 9 % %b7;'$7$ &+ % % ' 0% % $b'3(;567 7(67 - 9'' 9 * %b3//9'' &+ % $ ' 0% $ $b'3,17 7(67 . 9'' 9 & %b3//*1' &+ % $ ' 0% . $b'35;&/. 7(67 0 9'' 9 / %b(<(;< &+ % $ ' 0% % $b'35;' 7(67 7 9'' 9 1rwhv 5(6(59(' 0d\ kdyh lqwhuqdo flufxlw frqqhfwhg qr h[whuqdo frqqhfwlrq doorzhg rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-7 table 3-2. rl56csmv/3 pin signals by interface (continued) 7deoh &ro 7deoh 5rz /rf 6ljqdo ,) /rf 6ljqdo ,) /rf 6ljqdo ,) /rf 6ljqdo ,) 7 9'' 9 < *1' *1' & 5(6(59(' 7 9'' 9 < *1' *1' ' 5(6(59(' 8 9'' 9 $$ *1' *1' ' 5(6(59(' : 9'' 9 $$ *1' *1' ' 5(6(59(' < 9'' 9 $$ *1' *1' ' 5(6(59(' $$ 9'' 9 $$ *1' *1' ( 5(6(59(' $& 9'' 9 $$ *1' *1' ( 5(6(59(' $' 9'' 9 $$ *1' *1' ( 5(6(59(' $' 9'' 9 $$ *1' *1' ( 5(6(59(' $' 9'' 9 $% *1' *1' ( 5(6(59(' $' 9'' 9 $% *1' *1' ( 5(6(59(' $' 9'' 9 $% *1' *1' ( 5(6(59(' $' 9'' 9 $% *1' *1' ( 5(6(59(' $' 9'' 9 $ 5(6(59(' ( 5(6(59(' $' 9'' 9 $ 5(6(59(' ( 5(6(59(' $' 9'' 9 $ 5(6(59(' ( 5(6(59(' $( 9'' 9 $ 5(6(59(' ( 5(6(59(' $ 9** 9 $ 5(6(59(' ) 5(6(59(' 8 9** 9 $$ 5(6(59(' ) 5(6(59(' $$ 9** 9 $% 5(6(59(' ) 5(6(59(' ) *1' *1' $% 5(6(59(' ) 5(6(59(' ) *1' *1' $% 5(6(59(' * 5(6(59(' ) *1' *1' $% 5(6(59(' * 5(6(59(' ) *1' *1' $% 5(6(59(' * 5(6(59(' ) *1' *1' $( 5(6(59(' * 5(6(59(' ) *1' *1' $) 5(6(59(' * 5(6(59(' * *1' *1' % 5(6(59(' + 5(6(59(' * *1' *1' % 5(6(59(' + 5(6(59(' * *1' *1' % 5(6(59(' + 5(6(59(' * *1' *1' % 5(6(59(' + 5(6(59(' * *1' *1' % 5(6(59(' - 5(6(59(' * *1' *1' % 5(6(59(' - 5(6(59(' + *1' *1' % 5(6(59(' - 5(6(59(' + *1' *1' % 5(6(59(' - 5(6(59(' + *1' *1' % 5(6(59(' / 5(6(59(' + *1' *1' % 5(6(59(' 5 5(6(59(' + *1' *1' % 5(6(59(' 8 5(6(59(' + *1' *1' % 5(6(59(' 9 5(6(59(' : *1' *1' & 5(6(59(' : 5(6(59(' : *1' *1' & 5(6(59(' < 5(6(59(' : *1' *1' & 5(6(59(' : *1' *1' & 5(6(59(' : *1' *1' & 5(6(59(' : *1' *1' & 5(6(59(' : *1' *1' & 5(6(59(' < *1' *1' & 5(6(59(' < *1' *1' & 5(6(59(' < *1' *1' & 5(6(59(' < *1' *1' & 5(6(59(' < *1' *1' & 5(6(59(' 1rwhv 5(6(59(' 0d\ kdyh lqwhuqdo flufxlw frqqhfwhg qr h[whuqdo frqqhfwlrq doorzhg rl56csmv/3 and rl56csm/3 hardware interface description 3-8 conexant 1137 table 3-3. rl56csmv/3 signal definitions label i/o type signal name/description system overhead mcu_clkin it mcu clock in. connect to an external 40.0 mhz clock. dp_clkin itclk data pump clock in . connect to an external 28.224 mhz clock. mcu_reset# it/ot8 mcu reset. this active low input resets the modem to factory default values. after application of vdd, mcu_reset# must be held low for at least 2 ms after the vdd reaches operating range. the csmv/3 is ready to use 2 ms after the low-to-high transition of mcu_reset#. rome it mcu internal rom enable. active high input enables mcu internal rom access; low disables internal rom access. mcu_test# itpu mcu test mode. active low input enables test mode (factory test only). leave open for normal operation. vdd pwr digital supply voltage. connect to +3.3v. vgg pwr 5v reference voltage. vgg is the reference voltage for +5v tolerant inputs. connect to +5v if +5v tolerant inputs are required, otherwise, connect to vdd. gnd gnd digital ground. connect to digital ground. parallel host interface hba[5:1] it host bus address lines 1-5. during a host read or write operation with hbcs# low, hba[5:1] select one of 32 host bus registers. hbd[15:0] it/ot8 host bus data lines 0-15 . hbd[15:0] comprise 16 three-state input/output lines providing bidirectional communication between the host and the modem. data, control words, and status information are transferred over hbd[15:0]. hbclk itpu host bus clock. bus clock used to synchronize host bus accesses. hben# itpu host bus data output enable. when hbrd# low and hben# is low, the host data bus lines (hbd0- hbd15) are active; when hbrd# high and hben# high, the hbd0-hbd15 lines are tri-stated. hbrd# and hben# can be tied together. hbcs# itpu host bus chip select. hbcs# input low enables the host bus interface. hbrd# itpu host bus read. hbrd# is an active low read control input. when hbcs# is low, hbrd# low allows the host to read status information or data from the selected host bus register. hbwr# itpu host bus write. hbwr# is an active low write control input. when hbcs# is low, hbwr# low allows the host to write data or control words into the selected host bus register. hbackr# itpu host bus receive dma acknowledge. hbackr# is an active low input asserted to acknowledge receipt of hbrqstr by the host. hbackw# itpu host bus transmit dma acknowledge. hbackw# is an active low input asserted to acknowledge receipt of hbrqstw by the host. hbrqstr otts8 host bus receive dma request. hbrqstr is an active high output asserted to request dma transfer of received data. hbrqstw otts8 host bus transmit dma request. hbrqstw is an active high output asserted to request dma transfer of transmit data. hbirq# otts8 host bus interrupt request . hbirq# is an active low open drain output asserted to request host interrupt service. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-9 table 3-3. rl56csmv/3 signal definitions (contd) label i/o type signal name/description memory bus interface a0-a24 it/ot8 memory address lines 0-24. a0-a24 are the external memory bus address lines. connect a1-a12 to the sdram a0-a11 pins, respectively. d0-d15 it/ot8 memory data lines 0-15. d0-d15 are the external memory bus data lines. connect d0-d15 to the sdram d0-d15 pins, respectively. mcu_clkout otts8 mcu clock out. mcu_clkout is an output clock at mcu_clkin frequency. connect to the sdram clk pin. rd# otts8 read enable. rd# is an active low output used to enable data transfer from the selected device to the d0- d15 lines. not used with sdram. wr# otts8 write enable. wr# is an active low output used to enable data transfer from the d0-d15 lines to the selected device. not used with sdram. cs0-cs4 otts8 chip select line 0, 1, 2, 3, and 4. cs0-cs4 are active low chip select output lines used to select external memory. not used with sdram. bs[1:0] otts8 byte select lines 0 - 1. the bs output is used by the sdram to select the upper and lower bytes for 16-bit sdram access. connect bs0 to sdram dgml pin and bs1 to sdram dgmu pin. ras# otts8 row address strobe. ras# is an active low output used by the sdram to define the sdram operation commands in conjunction with the cas# and wr# signals and is latched by the sdram at the positive edge of clk. connect to sdram ras# pin. cas# otts8 column address strobe. cas# is an active low output to used by the sdram to define the sdram operation commands in conjunction with the ras# and wr# signals and is latched at the positive edge of clk. connect to sdram cas# pin. rw# itpu/ot8 read not write pulse. connect to we# of sdram. rl56csmv/3 and rl56csm/3 hardware interface description 3-10 conexant 1137 table 3-3. rl56csmv/3 signal definitions (contd) label i/o type signal name/description t1/e1 transceiver interface a_rxdata b_rxdata c_rxdata itk receive serial data. a-law/ m -law pcm receive data sample from the t1/e1 transceiver. a_txdata b_txdata c_txdata it/ot8 transmit serial data. a-law/ m -law pcm transmit data sample to the t1/e1 transceiver. tri-states when not shifting (figure 3-8). txdata requires a 33 ohm series resistor, to avoid problems caused by one driver turning off, while another driver is turning on. a_sclk b_sclk c_sclk itpu/ot2 clock. shift clock (1.544 mhz - 8.192 mhz) input from the t1/e1 transceiver. note: fsync and sclk must be operating whenever the device is not in reset. a_fsync b_fsync c_fsync itpu frame sync. 8 khz frame sync input from the t1/e1 transceiver. note: fsync and sclk must be operating whenever the device is not in reset. a_eyexy b_eyexy c_eyexy otts2 eye pattern x/y data output. not supported. no external connection. a_eyeclk# b_eyeclk# c_eyeclk# otts2 eye pattern clock output. not supported. no external connection. a_eyesync b_eyesync c_eyesync otts2 eye pattern sync output. not supported. no external connection. a_xclk b_xclk c_xclk it/ot2 xclk output. clock output at the data pump input frequency (dp_clkin). no external connection. a_yclk b_yclk c_yclk it/ot2 yclk output. clock output at one-half the data pump input frequency (dp_clkin) divided by two. a_pllvdd b_pllvdd c_pllvdd, pll pllvdd connection. connect to vdd through a 10 w resistor and to pllgnd through 0.1 m f and 10 m f capacitors in parallel. a_pllgnd b_pllgnd c_pllgnd pll pllgnd connection. connect to gnd. a_tsaen# b_tsaen# c_tsaen# itpu time slot assigner enable. these pins must be tied to ground to enable the time slot assigner. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-11 table 3-3. rl56csmv/3 signal definitions (contd) label i/o type signal name/description test/not used dp_test# itpu data pump test. factory test only. internal pull-up. leave open xycnt itpu xy control. factory test only. internal pull-up. leave open a_dpcs b_dpcs c_dpcs itpu data pump chip select. factory test only. internal pull-up. leave open a_dpexrst b_dpexrst c_dpexrst ith data pump external reset. factory test only; leave open. a_dpint b_dpint c_dpint itpu data pump interrupt. factory test only. internal pull-up. leave open a_dprst# b_dprst# c_dprst# ith data pump reset. connect to gnd through a 20k w resistor. a_dprxclk b_dprxclk c_dprxclk otts2 data pump receive data clock. factory test only; leave open. a_dprxd b_dprxd c_dprxd otts2 data pump receive data. factory test only; leave open. a_dptxclk b_dptxclk c_dptxclk otts2 data pump transmit data clock. factory test only; leave open. a_dptxd b_dptxd c_dptxd itpu data pump transmit data. factory test only; leave open. a_dspint b_dspint c_dspint it data pump dsp interrupt. factory test only. internal pull-up. leave open a_dsprst b_dsprst c_dsprst ith data pump dsp reset. factory test only; leave open. jtag test tck ij mcu test clock. this is the boundary scan clock signal of the microcontroller. this pin has an internal pulldown, and it conforms to ieee 1149.1 jtag specification. tdi ijpu mcu test input. this is the boundary scan serial input signal of the microcontroller, and it is shifted in on the rising edge of tck. the pin has an internal pullup, and it conforms to ieee 1149.1 jtag specification. tdo ojts4 mcu test output. this is the tristateable boundary scan data output signal from the microcontroller, and it is shifted out on the falling edge of tck. it conforms to ieee 1149.1 jtag specification. tms ijpu mcu test mode select. this is the control signal to the microcontroller tap controller. this pin has an internal pull-up, and it conforms to ieee 1149.1 jtag specification. trst# ijpu mcu test reset . a high to low signal forces the microcontroller tap controller into a logic reset state. it must be held low during normal (non-test) operation. this pin has an internal pull-up, and it conforms to ieee 1149.1 jtag specification. trst# requires a 3k ohm pull-down resistor to gnd. dpbs_tclk ij data pump test clock. this is the boundary scan clock signal for the internal data pumps. this pin does not have an internal pulldown. in an application design, connect to an external 50k w pulldown. it conforms to ieee 1149.1 jtag specification. dpbs_tdi ijpu data pump test input. this is the boundary scan serial input data for the internal data pumps. it is shifted in on the rising edge of dpbs_tck, and then daisy chained to all the data pumps. this pin has an internal pullup. it conforms to ieee 1149.1 jtag specification. dpbs_tdo ojts4 data pump test output. this tristateable boundary scan data output signal from the last daisy chained data pump. it is shifted out on the falling edge of dpbs_tck. it conforms to ieee 1149.1 jtag specification. rl56csmv/3 and rl56csm/3 hardware interface description 3-12 conexant 1137 table 3-3. rl56csmv/3 signal definitions (contd) label i/o type signal name/description dpbs_tms ijpu data pump test mode select. this is the control signal to the data pump tap controllers. this pin has an internal pullup. it conforms to ieee 1149.1 jtag specification. dpbs_trst# ijpu data pump test reset . a high to low signal forces the data pump tap controller into a logic reset state. this pin has an internal pullup and must be held low during normal (non-test) operation. it conforms to ieee 1149.1 jtag specification. dpbs_trst# requires a 3k ohm pull-down resistor to gnd. unassigned pa3 it/ot8 port pa3. not used; leave open. pa4 it/ot8 port pa4. not used; leave open. pa5 it/ot8 port pa5. not used; leave open. pa6 it/ot8 port pa6. not used; leave open. pa7 it/ot8 port pa7. not used; leave open. pe0 it/ot8 port pe0. not used; leave open. pe1 it/ot8 port pe1. not used; leave open. pe2 it/ot8 port pe2. not used; leave open. pe3 it/ot8 port pe3. not used; leave open. pe4 it/ot8 port pe4. not used; leave open. pe5 it/ot8 port pe5. not used; leave open. pe6 it/ot8 port pe6. not used; leave open. pe7 it/ot8 port pe7. not used; leave open. pf0 it/ot8 port pf0. not used; leave open. pf1 it/ot8 port pf1. not used; leave open. pf2 it/ot8 port pf2. not used; leave open. pf3 it/ot8 port pf3. not used; leave open. pf4 it/ot8 port pf4. not used; leave open. pf5 it/ot8 port pf5. not used; leave open. pf6 it/ot8 port pf6. not used; leave open. pf7 it/ot8 port pf7. not used; leave open. note: see i/o type descriptions in table 3-4. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-13 table 3-4. i/o type descriptions i/o type description reference ij +5v tolerant jtag input, c in = 8 pf pjd00n ijpu +5v tolerant jtag input, internal 75k 25k ohm pull-up, c in = 8 pf pjd00u it +5v tolerant ttl input, c in = 8 pf ptd00n it/ot2 +5v tolerant ttl input/ttl output, 2 ma into 120 ohm load, c in = 9 pf ptb01n it/ot8 +5v tolerant ttl input/ttl output, 8 ma into 50 ohm load, c in = 9 pf ptb03n itclk +5v tolerant ttl input, clock, internal keeper, c in = 22 pf ith +5v tolerant ttl input, hysterisis, c in = 8 pf ptd10n itk +5v tolerant ttl input, internal keeper, c in = 8 pf ptd00r itpd +5v tolerant ttl input, internal 75k 25k ohm pull-down, c in = 8 pf ptd00d itpu +5v tolerant ttl input, internal 75k 25k ohm pull-up, c in = 8 pf ptd00u itpu/ot2 +5v tolerant ttl-compatible input/ttl-compatible output (bidirectional), 2 ma into 120 ohm load, with 75k 25k ohm pull-up, c in = 9 pf ptb01ud itpu/ot8 +5v tolerant ttl input/ttl output (bidirectional), 8 ma into 50 ohm load, with 75k 25k ohm pull-up, c in = 9 pf ptb03u ojts4 +5v tolerant jtag 3-state output, 4 ma into 80 ohm load, c in = 10 pf pjt02n otts2 +5v tolerant ttl 3-state output, 2 ma into 120 ohm load, c in = 10 pf ptt01n otts8 +5v tolerant ttl 3-state output, 8 ma into 50 ohm load, c in = 10 pf ptt03n note : see digital electrical characteristics in table 3-5. rl56csmv/3 and rl56csm/3 hardware interface description 3-14 conexant 1137 table 3-5. digital electrical characteristics parameter symbol min. typ. max. units test conditions input voltage low v il -0.3 C 0.8 vdc input voltage high v ih 2.0 C 5.25 vdc vgg = 5v 2.0 C 3.6 vdc vgg = 3.3v input current low (see note 2) i il CC-10 av in = 0 input current high (see note 2) i ih CC+10av in = 5.25v input current low (with internal pull-downs) (see note 2) i il CC-10 av in = 0 input current high (with internal pull-downs) (see note 2) i ih C C +100 a v in = 5.25v input current low (with internal pull-ups) (see note 2) i il -15 C -100 a v in = 0 input current high (with internal pull-ups) (see note 2) i ih CC+10av in = 5.25v output voltage low v ol C C 0.4 vdc see note 3 output voltage high v oh 2.4 C vdd vdc see note 4 three-state (off) current low i ozl CC-10 av in = 0 three-state (off) current high i ozh CC+10av in = 5.25v notes: 1. test conditions: vdd = +3.3v 0.3v, ta = 0c to 70c, (unless otherwise stated). 2. current flow out of the device is shown as minus. 3. i ol = 8 ma for i/o types it/ot8, ot8, otts8, and itpu/ot8. i ol = 4 ma for i/o type it/ot4. i ol = 2 ma for i/o types it/ot2 and otts2. 4. i oh = -8 ma for i/o types it/ot8, ot8, otts8, and itpu/ot8. i oh = -4 ma for i/o type it/ot4. i oh = -2 ma for i/o types it/ot2 and otts2. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-15 3.2 electrical and environmental specifications 3.2.1 operating conditions and absolute maximum ratings operating conditions are stated in table 3-6. the absolute maximum ratings are listed in table 3-7. 3.2.2 current and power requirements the current and power requirements are listed in table 3-8. table 3-6. operating conditions parameter min. max. units vdd +3.0 +3.6 vdc vgg +4.75 +5.25 vdc ambient temperature (ta) 0 70 0 c table 3-7. absolute maximum ratings parameter symbol limits units supply voltage vdd -0.5 to +4.0 v input voltage v in -0.5 to (vgg +0.5) v operating temperature range t a -0 to +70 c storage temperature range t stg -55 to +125 c voltage applied to outputs in high impedance (off) state v hz -0.5 to (vgg + 0.5) v dc input clamp current i ik 20 ma dc output clamp current i ok 20 ma static discharge voltage (25c) v esd 2500 v latch-up current (25c) i trig 300 ma latch-up current (125c) i trig 150 ma latch-up current (25c) i trig 400 ma maximum junction temperature t j 125 c rl56csmv/3 and rl56csm/3 hardware interface description 3-16 conexant 1137 table 3-8. current and power requirements ddp clock at 28.224 mhz ddp clock at 45 mhz mode typ. current (ma) max. current (ma) typ. power (mw) max. power (mw) typ. current (ma) max. current (ma) typ. power (mw) max. power (mw) rl56csm/3 (r7138) normal mode 300 305 990 1100 na na na na sleep mode 163 540 rl56csmv/3 (r7178) normal mode 275 280 910 1010 330 333 1090 1200 sleep mode 152 500 152 500 notes: 1. current and power figures represent entire device (3 channels). 2. test conditions: vdd = 3.3 vdc for typical values; vdd = 3.6 vdc for maximum values. ta = 0c to 70c 3. f = internal operating frequency: mcu = 40 mhz; ddp = 28.224 mhz (during non-g.728 modes) or 45 mhz (during g.728 mode). the bga thermal characteristics are listed in table 3-9. table 3-9. thermal characteristics natural convection cooling forced convection cooling at 1 m/s die name die number t diff ( c) trise ( c) tmax ( c) tcase ( c) trise ( c) tmax ( c) tcase ( c) mcu 1 2.0 c27 9795 23 93 91 ddp 2, 3, and 4 2.0 c 22 92 90 17.5 87.5 85.5 notes: 1. the thermal performance of multi die bga packages is shown by temperature rise over the ambient temperature [ c] for different devices inside the package. the maximum operating junction temperature and case temperature can be estimated as follows: where: tambient = ambient temperature (specified at 70 c) measured 2 inches above the center of the package. tdiff = temperature difference between junction and case (specified for a given die). trise = temperature rise (specified for a given die for natural convection and forced convection at 1 m/s conditions). tmax = maximum operating junction temperature = tambient + trise [ c]. tcase = case temperature = tmax - tdiff.[ c]. example: hottest die; natural convection case with maximum tambient = 70 c: tdiff = 2.0 c (the case temperature for the hottest die is ~2.0 c lower than the maximum junction temperature). tmax = tambient + trise [ c] = 70 +27 = 97 c. tcase = tmax C tdiff [ c] = 97 - 2.0 = 95 c. 2. maximum allowable junction temperature = 125 c. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-17 3.2.3 thermal characteristics package thermal design and test structure figure 3-3 shows the internal structure of the multi-die ball grid array [bga] package. four die are mounted on a laminate substrate and over-molded for mechanical protection. the internal heat path transfers the heat from the top surface of the die to the bottom surface of the package through thermal vias and voltage planes. figure 3-3. multi die ball grid array package figure 3-3 and figure 3-4 show the primary heat flow path in a multi-die bga package. bga packa g e test board thermal vias die figure 3-4. package internal heat removal path thermal vias thermal balls ground plane figure 3-5. connecting bga thermal balls to motherboard ground plane by using thermal vias to obtain the best package thermal performance, connect the thermal balls to the motherboard ground plane, using thermal vias shown in figure 3-5. rl56csmv/3 and rl56csm/3 hardware interface description 3-18 conexant 1137 product thermal performance for multi-die packages, an equivalent thermal resistance is used to represent thermal performance. this definition is used to evaluate thermal performance of the package directly in a system level situation. the defined equivalent thermal resistance is only valid at the stated power conditions. junction temperature calculation for package type: 35 mm bga, size = 35.0 mm * 35.0 mm * 2.27 mm maximum junction temperature can be calculated as: t j = p q ja + t a (1) where: q ja = equivalent package thermal resistance (c/w) t j = maximum junction temperature(c) t a = ambient temperature (c) p = package total power dissipation value (w) for the rl56csm/3 (r7138) p = 1.190 (w) q ja = 19.55 c/w (natural convection) q ja = 15.20 c/w (1 m/s air flow) from equation (1) and assuming maximum ambient temperature of 70 c, maximum junction temperature for the natural convection case is calculated as: t j = 1.190 19.55 + 70 = 93.25 c for the rl56csmv/3 (r7178): p = 1.310 (w) q ja = 19.48 c/w (natural convection) q ja = 14.85 c/w (1 m/s air flow) from equation (1) and assuming maximum ambient temperature of 70 c, maximum junction temperature for the natural convection case is calculated as: t j = 1.310 19.48 + 70 = 95.50 c test structure package thermal performance has been tested following jedec standards. the bga package has been mounted at the center of a 100 mm x 100 mm 6-layer test board and has been tested under different air flow velocities. figure 3-6 shows the system configuration. b a l p l p a= 100 mm, b = 100 mm , l p = 2.27 mm and l b = 1.50 mm air flow figure 3-6. test performance structure rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-19 3.3 interface timing and waveforms 3.3.1 external sdram the csmv/3 requires connection to a 2 x 512k x 16-bit synchronous dynamic ram (sdram) meeting the intel pc100 spec. note: address a0-a11 of sdram connects to a1-a12 of rl56csm/3. the sdram interface waveforms are shown in figure 3-7 and interface timing is listed in table 3-10. tacs tacs toh tacs hdata sdata hbs sbs hrw srw hcas scas hadd sadd hras sras 11 01 11 row add col add wd0 wd1 wd2 wd3 wd4 10 rd0 rd1 mcu_clkout ras# & cs0# cas# rw# bs0 & bs1 a[12:1] d[15:0] write d[15:0] read 1194f3-3 wf-sdram figure 3-7. sdram interface timing table 3-10. sdram interface timing symbol parameter min. max. unit scas cas setup time 2.5 - ns hcas cas hold time 4 - ns sras ras setup time 2.5 - ns hras ras hold time 4 - ns srw rw setup time 2.5 - ns hrw rw hold time 4 - ns sbs bs setup time 2.5 - ns hbs bs hold time 4 - ns sadd address setup time 4.5 - ns hadd address hold time 4 - ns sdata data setup time 6.25 - ns hdata data hold time 4 - ns tacs sdram access time - 9 ns toh sdram output hold time 3 - ns rl56csmv/3 and rl56csm/3 hardware interface description 3-20 conexant 1137 3.3.2 t1/e1 transceiver interface timing the t1/e1 transceiver interface timing is listed in table 3-11 and waveforms are shown in figure 3-8. table 3-11. timing C t1/e1 transceiver parameter symbol min. max. unit sclk frequency fsck 1.0 12.0 mhz sclk duty cycle @ above 8 mhz 40 60 % @ equal or below 8 mhz 30 70 % fsync low time tf0 900 ns fsync high time tf1 900 ns fsync setup time relative to sclk falling edge tfs 10 ns fsync hold time relative to sclk falling edge tfh 10 ns txdata delay from sclk rising edge @ 50 pf tckdv 20 ns @ 200 pf 28 ns @500 pf 50 ns first txdata bit delay from fsync rising edge @ 50 pf tfsdv 20 ns @ 200 pf 28 ns @ 500 pf 50 ns rxdata setup time relative to sclk falling edge trs 10 ns rxdata hold time relative to sclk falling edge trh 10 ns txdata high-z output delay ttxhz 4 10 ns txdata low-z output delay ttxlz 4 10 ns test conditions: vdd = 3.3 0.3 vdc, ta = 0c to 70c. slot (n-1) slot 0 ttxhz tckdv tckdv tckdv tfsdv tckdv ttxlz trh trs tf1 tfh tf1 tf0 tfs tf0 msb 0 msb lsb msb-1 0 1 2 lsb 1 2 msb msb msb -1 sclk fsync txdata rxdata figure 3-8. tdm bus timing diagram to detect the rising edge of fsync, the ddp uses the falling edge of sclk (with tfs and tfh) to first sample fsync low. once fsync is detected low, the ddp looks for the rising edge of fsync. the next rising edges of fsync and sclk (with tckdv and tfsdv) determine the output of the first txdata data. after the first txdata bit of the first time slot, all subsequent txdata bits depend on the rising edge of sclk (and tckdv) only. note that the rising edge of fsync may occur earlier or later than the rising edge of the sclk. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-21 3.3.3 oscillator waveform requirements the oscillator waveform requirements are shown in figure 3-9. notes: 1. use care in pcb routing of mcu_clkin and mcu_clkout signals. minimize trace length, add terminations as required, and avoid impedance discontinuities to retain waveform integrity, i.e., maintain duty cycle, rise and fall times, and minimize undershoot and overshoot. 2. keep all traces and component leads connected to clock input and output pins short in order to reduce induced noise levels and minimize any stray capacitance that could affect the clock oscillator. 3. allow for a series impedance matching resistor at the clock source, and a parallel terminating resistor at the clock inputs. 4. use of a clock buffer driver is strongly recommended in order to meet rise and fall time requirements. tckh tckl 3.0 v 1.5 v 0 v [tckh/ ( tckh + tckl ) ]*100 = 45/55% figure 3-9. oscillator waveform requirements rl56csmv/3 and rl56csm/3 hardware interface description 3-22 conexant 1137 3.4 sdram interface connections 3.4.1 16-mbit sdram interface the interface connections to a 16-mbit sdram are shown in figure 3-10. +3.3v +3.3v bs0 cas# mcu_clkout rw# bs1 ras# cs1 rd# wr# nc nc nc r03 b11 a07 a12 n01 ae18 l01 p01 af21 ad20 b13 k01 a08 a14 a11 n03 af19 m03 ad24 ae20 ad18 b12 w26 a09 a13 l02 n02 ae19 m02 af22 p02 rl56csm/3 or rl56csmv/3 ad26 p25 a06 n24 nc nc b10 m01 a12 d2 a8 a5 a9 d3 a10 a1 d8 a11 a10 a4 a4 d0 d11 d4 d9 a7 a9 d15 a1 d12 d7 a3 a11 a2 a3 a5 a12 a[1..12] a6 d5 d13 d14 a8 d1 d10 a2 a7 d6 a6 16mbit sdram vcc 1 d0 2 d1 3 gndq 4 d2 5 d3 6 vccq 7 vccq 13 vccq 44 vccq 38 vcc 25 gndq 10 gndq 41 gndq 47 gnd 26 gnd 50 d4 8 d5 9 d6 11 d7 12 dqml 14 dqmu 36 ~we 15 ~cas 16 ~ras 17 ~cs 18 a0 21 a1 22 a2 23 a3 24 a4 27 a5 28 a6 29 a7 30 a8 31 a9 32 nc 33 nc 37 cke 34 clk 35 d8 39 a10/ap 20 a11 19 d9 40 d10 42 d11 43 d12 45 d13 46 d14 48 d15 49 figure 3-10. 16-mbit sdram interface connections rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 3-23 3.4.2 64-mbit sdram interface the interface connections to a 64-mbit sdram are shown in figure 3-11. +3.3v +3.3v bs0 cas# mcu_clkout rw# bs1 ras# cs1 rd# wr# nc nc nc nc nc or to +3.3v r03 b11 a07 a12 n01 ae18 l01 p01 af21 m01 ad20 b13 k01 a08 a14 a11 n03 af19 m03 ad24 ae20 ad18 b12 w26 a09 a13 l02 n02 ae19 m02 af22 p02 ad26 p25 a06 n24 b10 a12 rl56csm/3 or rl56csmv/3 d2 a8 a5 a9 d3 a10 a1 d8 a11 a10 a4 a4 d0 d11 d4 d9 a7 a9 d15 a1 d12 d7 a3 a11 a2 a3 a5 a6 d5 d13 d14 a8 d1 d10 a2 a7 d6 a6 a[1..11] 64mbit sdram ( 4x1mx16 ) vcc 1 d0 2 d1 4 gndq 6 d2 5 d3 7 vccq 3 vccq 9 vccq 49 vccq 43 vcc 14 gndq 12 gndq 46 gnd 41 gnd 54 d4 8 d5 10 d6 11 d7 13 dqml 15 dqmu 39 ~we 16 ~cas 17 ~ras 18 ~cs 19 a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 nc 36 nc 40 cke 37 clk 38 d8 42 a10/ap 22 a11 35 d9 44 d10 45 d11 47 d12 48 d13 50 d14 51 d15 53 a13 20 a12 21 gndq 52 gnd 28 vcc 27 figure 3-11. 64-mbit sdram interface connections rl56csmv/3 and rl56csm/3 hardware interface description 3-24 conexant 1137 this page is intentionally blank. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 4-1 4. host interface 4.1 registers and fifo the host interface (figure 4-1) is served by two fifos, one for transmitted data (outbound) from the host and one for received data (inbound) to the host. in addition to the fifos, there are four transmit and four receive mailbox registers tha t serve for out-of-band control data between the host and the microcontroller. status and interrupt control registers are also provided. each fifo is 128 bytes deep. the host interface is 16-bits wide, thus only 64 operations are required to read or write the entire fifo. the design of the fifos and associated registers allows simultaneous access by both the host and the microcontroller without the loss or modification of any data being exchanged. five host bus address inputs select one of 32 possible registers, 16 of which are reserved (table 4-1). host bus read, write and chip select signals are also input for control. external dma request and acknowledge signals are provided. the rx dma request is invoked when the fifo threshold has been reached. rx dma requests cease once the fifo has been emptied. receipt of a dma acknowledge signal forces assertion of the host chip select and the fifo address. when the dma acknowledge signal is active, the presence of the host read or write will transfer fifo data to or from the bus, respectively. similarly, the tx dma request is invoked when the tx_fifo is empty and continues until the fifo threshold has been reached. the request signals are active high and the acknowledge signals active low. rx_fifo tx_fifo host interface control arm mcu interface control dma ipb bus dma request dma acknowledge host data bus host addr bus 1-5 interrupt request mailbox interface figure 4-1. host interface block diagram rl56csmv/3 and rl56csm/3 hardware interface description 4-2 conexant 1137 table 4-1. host control, status and i/o registers host bus address register (read) register (write) 0x00 host tx_fifo data host tx_fifo data 0x01 host tx_fifo size host tx_fifo size 0x02 host tx_fifo threshold (low) host tx_fifo threshold (low) 0x03 host rx_fifo data host rx_fifo data 0x04 host rx_fifo size reserved 0x05 host rx_fifo threshold (high) host rx_fifo threshold (high) 0x06 host fifo control [15:0] host fifo control [15:0] 0x07 host fifo interrupt/acknowledge [15:0] host fifo interrupt/acknowledge [15:0] 0x08 txmail0 [15:0] txmail0 [15:0] 0x09 txmail1 [15:0] txmail1 [15:0] 0x0a txmail2 [15:0] txmail2 [15:0] 0x0b txmail3 [15:0] txmail3 [15:0] host write to this register will cause an interrupt to the csmv/3. csmv/3 acknowledge of this interrupt will cause a corresponding interrupt to the host 0x0c rxmail0 [15:0] reserved 0x0d rxmail1 [15:0] reserved 0x0e rxmail2 [15:0] reserved 0x0f rxmail3 [15:0] csmv/3 write to this register (csmv/3 address 0x10001de) will cause an interrupt to the host. the host acknowledge of this interrupt will cause a corresponding interrupt to the csmv/3. reserved rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 4-3 4.2 host interface description the csmv/3 host interface consists of two unidirectional 64x16 fifos, which allow the core processor in the csmv/3 and an external processor (host) to efficiently transfer data. the host interface has the following features: supports one wait state access on host side. supports 50 ns access speed on host side. supports dma request and acknowledge signals on both the csmv/3 and host interfaces. supports 8 bi-directional halfword mailboxes. supports threshold and time-out features on dma interface. the interface consists of four major blocks: csmv/3 interface control host interface control two fifo blocks mailbox interface. for consistent orientation purposes, the transmit (tx) direction is from a host computer to the pstn (public switched telephone network) and the receive (rx) direction is from the pstn to the host computer (figure 4-2). relative to the rl56csmv/3, tx data is received (read) from the host and transmitted (written) to the data pump and rx data is received (read) from the data pump and transmitted (written) to the host. transmit host computer receive tx-fifo mcu rxfifo ddp txd rxd rxd txd txd rxd rxd txd txd rxd figure 4-2. reference direction for modem data rl56csmv/3 and rl56csm/3 hardware interface description 4-4 conexant 1137 4.2.1 mailbox interface the mailbox interface consists of eight registers, all of which can be read or written by either the host or the csmv/3. the first four are txmail0-txmail3 and the second four are rxmail0-rxmail3. normally, the txmail registers are written by the host and read by the csmv/3, and the rxmail registers are written by the csmv/3 and read by the host. txmail3 has a special feature such that a mailbox write interrupt request is triggered to the csmv/3 processor when the host writes to txmail3. a mailbox acknowledge interrupt is asserted to the host processor when the csmv/3 acknowledges the txmail3 interrupt, similarly, the csmv/3 writing to rxmail3 will interrupt the host, and the host acknowledge of that interrupt will trigger an interrupt to the csmv/3. 4.2.2 host fifo interface the host fifo interface control section is used to control the access to the fifo by the host processor. tx_fifo host interface the tx_fifo host interface consists of the following registers which are accessible by the host: txfifo data[15:0] used to write data into the fifo. reading this register returns last value written. txfifo size[15:0] the current depth of the fifo. txfifo threshold the low threshold value of the tx_fifo. a tx_fifo depth less than this value will cause an interrupt to occur to the host if enabled. this value can also be used to control the external dma request line. the dma can be used to fill the fifo. once the fifo is full the dma request signal is de-asserted. if the dma threshold feature is active, then the dma request signal will not be reasserted until the csmv/3 has removed enough data so that the depth of the fifo is less than the low threshold. once the dma request is asserted, the dma will completely fill the fifo or empty the dma buffer, whichever occurs first. once the tx_fifo is full the dma request line will again be de-asserted. rx_fifo host interface the rx_fifo host interface consists of the following registers: rxfifo data[15:0] used to read data from the fifo. this register cannot be written. rxfifo size[15:0] the current depth of the receive fifo. rxfifo threshold the high threshold value of the rx_fifo. exceeding this value will cause an interrupt to occur to the host if enabled. the interrupt cannot be cleared until sufficient data has been removed from the fifo by the host to cause the size to be less than the threshold. this value can also be used to control the external dma request line. the dma can be used to empty the rx_fifo. once the fifo is empty the dma request signal is de-asserted. if the dma threshold feature is active, then the dma request signal will not be re-asserted until the csmv/3 has written enough data so that the depth of the fifo is greater than the high threshold. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 4-5 host fifo control the host fifo control register contains control (enable) bits for the host transmit and receive fifo and the mailbox interface. 76543210 dmamode rxdhe hbrxrq_en rxff_en reserved txdhe hbtxrq_en txff_en 15 14 13 12 11 10 9 8 reserved rxm3ie rxthie rxfie dmabeie txm3ie txthie txeie bit 0 txff_en enables tx_fifo operation. the fifos are disabled on reset. bit 1 hbtxrq_en enables operation of hbrqstw. bit 2 txdhe tx_fifo dma hysteresis enable. bit 3 reserved bit 4 rxff_en enables rx_fifo operation. the fifos are disabled on reset. bit 5 hbrxrq_en enables operation of hbrqstr. when disabled the output is low. bit 6 rxdhe rx_fifo dma hysteresis enable. bit 7 dmamode enables one of two dma modes. see following explanation. bit 8 txeie tx_fifo empty interrupt enable. bit 9 txthie tx_fifo threshold interrupt enable. bit 10 txm3ie txmail3 interrupt enable. bit 11 dmabeie internal rx dma buffer empty interrupt enable. also, this condition will trigger the hbrqstr signal without reaching the threshold. bit 12 rxfie rx_fifo full interrupt enable. bit 13 rxthie rx_fifo threshold interrupt enable. bit 14 rxm3ie rxmail3 interrupt enable. bit 15 reserved dmamode = 0 (bit 7) 1. hbrqstr is deasserted when the last word read by the host empties the rx_fifo. 2. hbrqstw is deasserted when the last word written by the host causes the tx_fifo level to exceed the csmv/3 tx_fifo threshold(high) when hysteresis is enabled. 3. in this mode the action required to read or write the fifos is a toggle of the corresponding hbackr#/hbackw# signals. 4. data may be read (or written) by toggling, at least one cycle on and one cycle off, the hbrd# (or hbwrp). data may also be transferred by toggling the appropriate acknowledge signal. rl56csmv/3 and rl56csm/3 hardware interface description 4-6 conexant 1137 dmamode = 1 (bit 7) 1. hbrqstr is deasserted when two words remain to be read from the rx_fifo. 2. hbrqstw is deasserted when the last word written by the host causes the tx fifo level to equal two words less than the csmv/3 tx_fifo threshold(high) when hysteresis is enabled. 3. the csmv/3 device will read or write one word of host data every two hbclk clock cycles as long as the associated acknowledge signal is active (low). the hbcs# and hbrd# or hbwr# are not required during the period the acknowledge signal is asserted. in this mode when reading the rx_fifo, hbackr# asserted, it is required that the hben# signal be asserted to enable the output drivers. hben# should be high during periods when hbackw# is asserted. host fifo int/ack this register contains fifo status indicator bits as well as corresponding acknowledge bits. the host writing to bits 8-15 will have no affect since these bits are set by fifo logic. the fifo interrupt acknowledge bits, 0-6, are used to clear the corresponding interrupt. any or all bits may be acknowledged simultaneously. writing a one to the corresponding interrupt acknowledge bit causes the status bit to be cleared and the corresponding interrupt deasserted if currently active. writing a zero to any bit has no effect. bit 7 is provided as an optional means of the host causing the csmv/3s internal dma to read the tx_fifo. if the data level in the fifo has not reached the csmv/3 tx_fifo threshold, then setting this bit will cause the csmv/3 internal dma request signal to be asserted. 76543210 txcmplt rxm3iak rxthiak rxfiak dmabeak txm3iak txthiak txeiak 15 14 13 12 11 10 9 8 reserved rxm3i rxth rxf dmabei txm3i txth txe bit 0 txeiak writing a 1 clears the corresponding interrupt status bit. bit 1 txthiak writing a 1 clears the corresponding interrupt status bit. bit 2 txm3iak writing a 1 clears the corresponding interrupt status bit. bit 3 dmabeiak writing a 1 clears the corresponding interrupt status bit. bit 4 rxfiak writing a 1 clears the corresponding interrupt status bit. bit 5 rxthiak writing a 1 clears the corresponding interrupt status bit. bit 6 rxm3iak writing a 1 clears the corresponding interrupt status bit. bit 7 txcmplt writing a 1 will set the csmv/3 threshold interrupt status. bit 8 txe the tx_fifo is empty. bit 9 txth the tx_fifo depth is less than the threshold value. bit 10 txm3i the csmv/3 has acknowledged a txm3 full interrupt. bit 11 dmabei the dma buffer is empty. bit 12 rxf the rx_fifo is full. bit 13 rxth the rx_fifo depth is greater than the threshold value. bit 14 rxm3i the csmv/3 has written data to the rxmail3 register. bit 15 reserved rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 4-7 4.2.3 host bus timing host read the host bus read timing is listed in table 4-2 and illustrated in figure 4-3. to read, the host first asserts the chip select hbcs#, hba[5:1] and hben# to request the csmv/3 host bus. hben# must be asserted at least one cycle before the end of the hbrd# signal to turn on the data output drivers. the csmv/3 will then output data on hbd[15:0]. the hbcs# or hbrd# must be deasserted for one cycle following a read operation before a subsequent read or write may occur. table 4-2. timing - host read parameter symbol min max units clock period t cyc 25 ns address to data valid t as 20 ns address hold t ah 2ns chip select to data valid t cs 20 ns chip select hold t ch 2ns chip select pulse width t csw t cyc ns bus enable to low impedance t en 14 ns bus enable hold t enh 2ns read pulse to data valid t dd 20 ns read pulse hold t rdh 2ns read pulse width t rdw t cyc ns data tristate delay t dz 5ns test conditions: vdd = 3.3 0.3 vdc, ta = 0c to 70c, output load = 45 pf. hbd[15:0] hben# hba[5:1] hbrd# hbcs# t cyc addr 1 addr 2 addr 3 t as t rdw t en hbclk data 2 data 3 data 1 t dd t ah t dz t enh t rdh t ch t csw t cs addr 4 data 4 1194f4-3 w f hr figure 4-3. waveforms - host read rl56csmv/3 and rl56csm/3 hardware interface description 4-8 conexant 1137 host write host write timing is listed in table 4-3 and illustrated in figure 4-4. host writes are similar to the reads except that hbwr# is taken low, and the hbd[15:0] data is supplied by the host. data will be clocked into the csmv/3 on the rising edge of the hbclk. hbcs# or hbwr# must be deasserted for one cycle before a subsequent read or write can occur. table 4-3. timing - host write parameter symbol min max units clock period t cyc 25 ns address valid to clock rising edge t as 20 ns address hold t ah 2ns chip select to clock rising edge t cs 20 t cyc *ns chip select hold t ch 2ns write pulse to clock rising edge t wr 20 t cyc *ns write pulse hold t wh 2ns data valid to clock rising edge t ds 18 ns data write hold t dh 2ns *the host chip select or write pulse must be deactivated prior to the second rising edge of the clock to prevent latching the data bus a second time. test conditions: vdd = 3.3 0.3 vdc, ta = 0c to 70c, output load = 45 pf. hbd[15:0] hben# hba[5:1] hbcs# t cyc addr 1 addr 2 addr 3 t as t cs hbclk t dh data 1 data 2 data 3 hbwr# t w r t ds t ch t w h t ah 1194f4-4 w f h w addr 4 data 4 figure 4-4. waveforms - host write rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 4-9 4.2.4 host interface - dma demand mode timing dma demand mode is entered when the control bit dmamode is set. the dmamode = 1 setting selects a burst type of data transfer controlled by the host acknowledge signal. for this activity to occur it is necessary that the associated hbtxrq_en or hbrxrq_en be set (enabled). in this mode the action of asserting the hbackr# (or hbackw#) will: 1. ignore the setting of the control and address signals, hba[5:1], hbcs#, hbrd# (or hbwr#). 2. data from the fifo will be output on every other hbclk cycle (note: the host data bus transfer rate cannot exceed 50 ns per word. therefor the minimum hbclk period cannot be less than 25 ns. 3. during the period when hbackr# (or hbackw#) is active, no other host registers may be accessed. in systems with multiple csmv/3s, the hbackr#( or hbackw#) signal can be bussed to all devices as long as only one device has its hbtxrq_en or hbrxrq_en enabled at any one time. also, in dmamode = 1, the host should set the fifo threshold value at the desired level and the fifo hysteresis mode must be enabled. host dma demand mode read the host dma demand mode read timing is shown in figure 4-5. hbackr# hbrqstr hbd0-15 hba1-5 hbrd# hbcs# t hben# t cyc hbclk rd data 1 data 2 data data n-1 data n n-2 figure 4-5. host dma demand mode read, dmamode = 1 rl56csmv/3 and rl56csm/3 hardware interface description 4-10 conexant 1137 host dma demand mode write the host dma demand mode write timing is shown in figure 4-6. hbackw# hbrqstw hbd0-15 hba1-5 hbwr# hbcs# hben# t cyc hbclk t ds data 1 data 2 data n-2 data n-1 data n t cyc + t dh figure 4-6. host dma demand mode write, dmamode = 1 rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 4-11 4.2.5 host interface pin summary a summary of the csmv/3 host interface inputs and outputs is shown in table 4-4. table 4-4. host bus interface pin description pin description function hba[5:1] host bus address input hbd[15:0] host bus data i/o hbrd# host bus read not - when low, the host is reading data from the csmv/3. i hbwr# host bus write not - when low, the host is writing data to the csmv/3. i hbcs# host bus chip select not i hbclk host bus clock i hben# host bus data output enable not - used in conjunction with hbrd# low or hbackr# low. if hben# is low then hbd is active, if high then hbd is tri-stated. i hbirq# host bus interrupt request - interrupt from the csmv/3 to the host. o hbrqstw host bus transmit dma request o hbackw# host bus transmit dma acknowledge i hbrqstr host bus receive dma request o hbackr# host bus receive dma acknowledge i rl56csmv/3 and rl56csm/3 hardware interface description 4-12 conexant 1137 this page is intentionally blank. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 5-1 5. design considerations good engineering practices must be followed when designing a printed circuit board (pcb) containing the modem device. this is especially important considering the high data bit rate and high fax rate. suppression of noise is essential to the proper operation and performance of the modem. two aspects of noise in an oem board design containing the modem device set must be considered: on-board/off-board generated noise that can affect modem operation and on-board generated noise that can radiate off-board. both on-board and off-board generated noise that is coupled on-board can affect interfacing signal levels and quality. of particular concern is noise in frequency ranges affecting modem performance. on-board generated electromagnetic interference (emi) noise that can be radiated or conducted off-board is a separate, but equally important, concern. this noise can affect the operation of surrounding equipment. most local governing agencies have stringent certification requirements that must be met for use in specific environments. in order to minimize the contribution of the circuit design and pcb layout to emi, the designer must understand the major sources of emi and how to reduce them to acceptable levels. proper pc board layout (component placement and orientation, signal routing, trace thickness and geometry, etc.), component selection (composition, value, and tolerance), interface connections, and shielding are required for the board design to achieve desired modem performance and to attain emi certification. all the aspects of proper engineering practices are beyond the scope of this designer's guide. the designer should consult noise suppression techniques described in technical publications and journals, electronics and electrical engineering text books, and component supplier application notes. seminars addressing noise suppression techniques are often offered by technical and professional associations as well as component suppliers. the following guidelines are offered to specifically help achieve stated modem performance and to minimize emi generation. 5.1 pc board layout guidelines 5.1.1 general principles 1. keep high speed digital traces as short as possible. 2. provide proper power supply distribution, grounding, and decoupling. 3. provide separate digital ground and chassis ground (if appropriate) planes. 4. provide wide traces for power and critical signals. 5. position interface digital circuits near the corresponding host bus connection. 5.1.2 component placement 1. from the system circuit schematic, a) identify the high speed digital circuits and their components, as well as external signal and power connections. b) note the location of power and signals pins for each device (ic). 2. once sections have been roughly defined, place the components starting with the connectors and jacks. a) allow sufficient clearance around connectors and jacks for mating connectors and plugs. b) allow sufficient clearance around components for power and ground traces. c) allow sufficient clearance around sockets to allow the use of component extractors. 3. place active digital components/circuits and decoupling capacitors. a) place digital components close together in order to minimize signal trace length. b) place 0.1 f decoupling (bypass) capacitors close to the pins (usually power and ground) of the ic they are decoupling. make the smallest loop area possible between the capacitor and power/ground pins to reduce emi. c) place crystal/clock circuits as close as possible to the devices they drive. 5.1.3 signal routing 1. keep host interface signals (e.g., hbcs#, hbrd#, hbwr#, and reset#) traces at least 10 mil thick (preferably 12 - 15 mil). rl56csmv/3 and rl56csm/3 hardware interface description 5-2 conexant 1137 2. keep all other signal traces as wide as possible, at least 5 mil (preferably 10 mil).route the signals between components by the shortest possible path (the components should have been previously placed to allow this). 3. route the traces between bypass capacitors to ic pins, at least 25 mil wide; avoid vias if possible. 4. avoid right angle (90 degree) turns on high frequency traces. use smoothed radiuses or 45 degree corners. 5. minimize the number of through-hole connections (feedthroughs/vias) on traces carrying high frequency signals. 6. keep all signal traces away from crystal/clock circuits. 7. distribute high frequency signals continuously on a single trace rather than several traces radiating from one point. 8. provide adequate clearance (e.g., 60 mil minimum) around feedthroughs in any internal planes. 9. eliminate ground loops, which are unexpected current return paths to the power source. 5.1.4 power 1. identify digital power (vdd) supply connections. 2. place a 10 f electrolytic or tantalum capacitor in parallel with a ceramic 0.1 f capacitor between power and ground at one or more points in the digital section. place one set nearest to where power enters the pcb (edge connector or power connector) and place another set at the furthest distance from where power enters the pcb. these capacitors help to supply current surge demands by the digital circuits and prevent those surges from generating noise on the power lines that may affect other circuits. 3. for 2-layer boards, route a 200-mil wide power trace on two edges of the same side of the pcb around the border of the circuits using the power. (note that a digital ground trace should likewise be routed on the other side of the board.) 4. generally, route all power traces before signal traces. 5.1.5 ground planes 1. in a 2-layer design, provide digital ground plane areas in all unused space around and under digital circuit components on both sides of the board and connect them such a manner as to avoid small islands. connect each ground plane area to like ground plane areas on the same side at several points and to like ground plane areas on the opposite side through the board at several points. connect all modem dgnd pins to the digital ground plane area. 2. in a 4-layer design, provide a digital ground plane covering the corresponding digital circuits. connect all modem gnd pins to the digital ground plane. 3. in a design which needs emi filtering, define an additional chassis section adjacent to the bracket end of a plug-in card. most emi components (usually ferrite beads/capacitor combinations) can be positioned in this section. fill the unused space with a chassis ground plane, and connect it to the metal card bracket and any connector shields/grounds. 4. keep the current paths of separate board functions isolated, thereby reducing the current's travel distance. separate board functions are: host interface, display, and digital (sram, eprom, modem). power and ground for each of these functions should be separate islands connected together at the power and ground source points only. 5. connect grounds together at only one point, if possible, using a ferrite bead. allow other points for grounds to be connected together if necessary for emi suppression. 6. keep all ground traces as wide as possible, at least 25 mil to 50 mil. 7. keep the traces connecting all decoupling capacitors to power and ground at their respective ics as short and as direct (i.e., not going through vias) as possible. 5.1.6 clock oscillator circuit 1. use +3.3 v oscillators with specified 45/55% duty cycle limits C this is critical for mcu_clkin. 2. use care in pcb routing of mcu_clkin and mcu_clkout signals. minimize trace length, add terminations as required, and avoid impedance discontinuities to retain waveform integrity, i.e., maintain duty cycle, rise and fall times, and minimize undershoot and overshoot. 3. maintain +3.3v supply within 10%. 4. keep all traces and component leads connected to clock input and output pins short in order to reduce induced noise levels and minimize any stray capacitance that could affect the clock oscillator. 5. allow for a series impedance matching resistor at the clock source, and a parallel terminating resistor at the clock inputs. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 5-3 5.1.7 emi considerations for standalone modem design 1. use a metal enclosure. 2. if a plastic enclosure is required, internal metal foil lining the enclosure or conductive spray applied to the top and bottom covers may reduce emissions. 5.1.8 optional configurations because fixed requirements of a design may alter emi performance, guidelines that work in one case may deliver little or no performance enhancement in another. initial board design should, therefore, include flexibility to allow evaluation of optional configurations. these optional configurations may include: 1. chokes that can replaced with jumper wires as a cost reduction if the design has sufficient emi margin. 2. various grounding areas connected by tie points (these tie points can be short jumper wires, solder bridges between close traces, etc.). 3. cable ground wires or cable shielding connected on the board or floated. 4. develop two designs in parallel; one based on a 2-layer board and the other based on a 4-layer board. during the evaluation phase, better performance of one design over another may result in quicker time to market. 5.1.9 ddp specific 1. provide a 0.1 f ceramic decoupling capacitor to ground between the power supply and the vdd pins. rl56csmv/3 and rl56csm/3 hardware interface description 5-4 conexant 1137 5.2 oscillator specifications recommended surface-mount clock oscillator specifications are listed in table 5-1. recommended through-hole clock oscillator specifications are listed in table 5-2. table 5-1. clock oscillator specifications - surface mount characteristic value value electrical output frequency 28.224 mhz 40.000 mhz nom. frequency stability (note 1) 100 ppm (0c to 70c) 100 ppm (0c to 70c) symmetry 45 / 55% 45 / 55% output voltage vdd max. 2.4v min. vdd max. 2.4v min. rise/fall time (note 2) 6 ns max. 6 ns max. (note 3) driving ability 10 ttl load or 50 pf hcmos load 10 ttl load or 50 pf hcmos load start up time 3 ms typ. 3 ms typ. supply voltage 3.3v 0.3v 3.3v 0.3v supply current (note 4) 45 ma max. 50 ma max. storage temperature C55c to 125c C55c to 125c mechanical dimensions (l x w x h) 7.64 x 5.23 x 1.95 mm max. 7.64 x 5.23 x 1.95 mm max. mounting smt smt package ceramic (leadless chip carrier) ceramic (leadless chip carrier) suggested suppliers kds america kds america ilsi america ilsi america vectron technologies, inc. vectron technologies, inc. notes: 1. inclusive of calibration tolerance @ 25c, over the operating temperature range, and aging. 2. transition times are measured between 10% and 90% of supply voltage. 3. a transition time of 6 ns is acceptable if the clock buffer can supply the waveform shown in figure 3-9. 4. current consumption is typically 0.4 ma/mhz above 20 mhz frequencies. 5. suggested suppliers: kds america fountain valley, ca 92626 (714) 557-7833 ilsi america kirkland, wa 98033 (206) 828 - 4886 vectron technologies, inc. lowell, nh 03051 (603) 598-0074 rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 5-5 table 5-2. clock oscillator specifications - through hole characteristic value value electrical output frequency 28.224 mhz 40.000 mhz nom. frequency stability (note 1) 100 ppm (0c to 70c) 100 ppm (0c to 70c) symmetry 45 / 55% max. 45 / 55% max. output voltage vdd max. 2.4v min. vdd max. 2.4v min. rise/fall time (note 2) 6 ns max. 6 ns max. (note 3) driving ability 10 ttl load or 50 pf hcmos load 10 ttl load or 50 pf hcmos load start up time 3 ms typ. 3 ms typ. supply voltage 3.3v 0.3v 3.3v 0.3v supply current (note 4) 45 ma max. 45 ma max. storage temperature C55c to 125c C55c to 125c mechanical dimensions (l x w x h) 13.2 x 13.2 x 5.0 mm max. 13.2 x 13.2 x 5.0 mm max. mounting through hole through hole package half size 8-pin dip half size 8-pin dip notes: 1. inclusive of calibration tolerance @ 25c, over the operating temperature range, and aging. 2. transition times are measured between 10% and 90% of supply voltage. 3. a transition time of 6 ns is acceptable if the clock buffer can supply the waveform shown in figure 3-9. 4. current consumption is typically 0.4 ma/mhz above 20 mhz frequencies. 5. suggested suppliers: kds america fountain valley, ca 92626 (714) 557-7833 ilsi america kirkland, wa 98033 (206) 828 - 4886 vectron technologies, inc. lowell, nh 03051 (603) 598-0074 rl56csmv/3 and rl56csm/3 hardware interface description 5-6 conexant 1137 5.3 package dimensions package dimensions are shown in figure 5-1. rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 5-7 figure 5-1. package dimensions - 340-pin bga rl56csmv/3 and rl56csm/3 hardware interface description 5-8 conexant 1137 5.4 plastic bga handling and use 5.4.1 handling plastic bga (pbga) packages are more robust than quad flat pack (qfp) packages. touching or knocking the solder ball will not cause a bent solder ball. as with all packages, the devices should be treated as electrostatic damage (esd) sensitive and the solder contacts shall be kept clean from dirt or oils. pbgas are typically transported and protected in trays and dry packe d for moisture protection 5.4.2 circuit card design circuit boards designed for pbga packages should adhere to the following guidelines. solder pad design plated through holes must not be placed in the pad which is intended to attach a solder ball. this will cause the solder to wic k inside the hole and produce misformed balls and electrical opens. instead any plated through holes should be placed away from the attach pad. tenting the via will prevent misaligned balls from wicking into the via. plugging the vias further prevent s solder ball wicking as well as trapped flux contamination. solder mask defined (smd) pads or non-solder mask defined (nsmd) pads are both suitable pad designs (see figure 5-2). typical smd design has a copper pad 30 mils (0.76 mm) diameter with a solder mask opening of 25 mils (0.63 mm). for routing escape, nsmd designs have a copper pad of 25 mils (0.63 mm) down to 20 mils (0.51 mm) with the solder mask opening 5 mils (0.13 mm) larger than the copper pad. nsmd pads provide easy x-ray inspection of the solder ball wetting to the pad tail and have excellent thermal cycle fatigue life. nsmd pads, however, have less strength than smd pads and may not be suitable for boards which undergo significant bending or twisting.(). figure 5-2. plated hole placement guideline for connection to bga ball pbga placement design pbga packages should be placed on the printed circuit board with manufacturability in mind. if a pbga is to be removed, it is usually done with a hot air nozzle. some spacing (50 mils minimum) should be allowed between adjacent devices. if components are wave soldered, these devices should be placed away from the pbga to prevent the wave from reflowing or washing away the solder balls. if the pbga is mount on top, plated-through-holes under the pbga should be tented or plugged before bottom side wave soldering. 5.4.3 solder reflowing solder pad preparation ball attach pads most often have solder paste screen printed or stenciled for reflow preparation. paste application is most popular using stencils with 6 mil to 8 mil thicknesses and 20 to 25 mil openings. in addition, pbgas can be assembled with flux only (no solder paste is required). no-clean paste or flux is most popular, although rosin and water soluble fluxes are al so usable. temperature profiling when establishing a reflow profile, it is necessary to monitor the temperature of each pbga location on the circuit board as well as across the individual pbgas. a good technique for measuring pbga temperature is to drill several small holes rl56csmv/3 and rl56csm/3 hardware interface description 1137 conexant 5-9 through the top of the package just to the solder balls. insert thermocouples into these hole. then, fill the holes and tack down the wires with epoxy. thermocouples should be placed above outer corner balls (typically the hottest) and the most inner balls (typically the coolest). ideal reflow profiles should be developed around the solder paste or flux. typically profiles elevate the pbga above the tin- lead liquidus temperature of 183c for 60 seconds and a peak temperature between 205c and 220c. solder ball temperatures above 230c create higher risks for popcorn delamination. full convection forced air furnaces provide the most uniform temperature, however, infrared or vapor phase systems can be used. nitrogen gas is not required but can be used to improve yields in cases of poor printed circuit board wettability or process enhancement. if a hot air nozzle is used to attach the pbga, heat the entire circuit board with a secondary hot plate or hot air during the reflow process. preheating the entire board will make the pbga attach process much faster and minimize thermal shock to the package and circuit board. placement due to the "self alignment" nature of pbgas, placement accuracy can be as coarse as + 12 mils or greater and still have the package reflow into position. for greatest accuracy, package placement should be referenced off of the solder balls. this can be performed with standard bottom side vision systems which align the solder balls to the pads or with a simple nesting plate which keys off the solder balls. referencing off of the pbga body is also suitable. 5.4.4 inspection due to the robust nature of pbga solder reflow, in-line inspection is not required for production assembly. if uniform reflow temperature is maintained and outer solder joints look good, the internal joints will be good. standard two-dimensional x-rays are extremely useful when initially characterizing a soldering process or trouble shooting electrical failures. x-rays often determine that electrical failures blamed on the pbga are really caused by other components. 5.4.5 rework and removal precaution must be used when removing moisture sensitive pbga packages or non bga packages close to the rework site. if the board contains moisture sensitive packages near the rework location, the entire board should be baked at least 12 hours at 125c prior to any rework. pbga rework is most commonly performed with hot air rework stations. the most effective stations provide bottom side preheating (for the entire circuit board) and a programmable temperature/time profile. after a pbga is removed, excess solder will remain on the circuit board and the package balls will be destroyed. this excess solder on the board must be removed to prepare the solder pads. a solder vacuum tool works best to prevent damaged pads usually caused with solder wicks or excessively hot soldering irons. after the pads are cleaned, the same flux as was used during the initial soldering should be applied to the pads. the new pbga should then be aligned on the pads and reflowed using the same hot air profile. as with any pbga, care must be take never to touch or push down of the package while the solder balls are molten. this action will cause the balls to squash and bridge with adjacent balls. removed pbgas may either be reballed for reuse (if determined good) or scrapped. 5.4.6 moisture pbgas are considered to be moisture sensitive and require baking and sealing in a bag called dry pack. if packages are allowed to absorb moisture, then they risk popcorning or cracking during solder reflow. standard moisture ratings for pbga packages (level 4) recommend devices be assembled within 72 hours after they are removed from the dry pack bag. if this time is exceeded, then the parts should be baked at least 12 hours at 125c prior to assembly. 5.4.7 references petrucci, ramirez and brown, high volume smt assembly of high pin count pbga devices, proceedings of the technical program, smi 1995, pp.297-304. dody and burnette, bga assembly process and rework, proceedings of the technical program, smi 1995, pp.361-366. johnston, printed circuit board design guidelines for ball grid array packages, proceedings of the technical program, smi 1995, pp.255-360. jones, increasing bga manufacturing yields, electronic packaging & production, feb 1996, pp38-46. jedec standard test method a112: moisture-induced stress sensitivity for plastic surface mount devices, jesd22-a112, april 1994. rl56csmv/3 and rl56csm/3 hardware interface description 5-10 conexant 1137 this page is intentionally blank. inside back cover notes further information literature@conexant.com 1-800-854-8099 (north america) 33-14-906-3980 (international) web site www.conexant.com world headquarters conexant systems, inc. 4311 jamboree road p. o. box c newport beach, ca 92658-8902 phone: ( 949) 483-4600 fax: (949) 483-6375 u.s. florida/south america phone: ( 727) 799-8406 fax: (727) 799-8306 u.s. los angeles phone: ( 805) 376-0559 fax: (805) 376-8180 u.s. mid-atlantic phone: ( 215) 244-6784 fax: (215) 244-9292 u.s. north central phone: ( 630) 773-3454 fax: (630) 773-3907 u.s. northeast phone: ( 978) 692-7660 fax: (978) 692-8185 u.s. northwest/pacific west phone: ( 408) 249-9696 fax: (408) 249-7113 u . s. south central phone: ( 972) 733-0723 fax: (972) 407-0639 u.s. southeast phone: ( 919) 858-9110 fax: (919) 858-8669 u.s. southwest phone: ( 949) 483-9119 fax: (949) 483-9090 apac headquarters conexant systems singapore, pte. ltd. 1 kim seng promenade great world city #09-01 east tower singapore 237994 phone: (65) 737 7355 fax: (65) 737 9077 australia phone: (61 2) 9869 4088 fax: (61 2) 9869 4077 china phone: (86 2) 6361 2515 fax: (86 2) 6361 2516 hong kong phone: ( 852) 2827 0181 fax: (852) 2827 6488 india phone: (91 11) 692 4780 fax: (91 11) 692 4712 korea phone: (82 2) 565 2880 fax: (82 2) 565 1440 phone: (82 53) 745 2880 fax: (82 53) 745 1440 europe headquarters conexant systems france les taissounieres b1 1681 route des dolines bp 283 06905 sophia antipolis cedex france phone: (33 1) 41 44 36 50 fax: (33 4) 93 00 33 03 europe central phone: (49 89) 829 1320 fax: (49 89) 834 2734 europe mediterranean phone: (39 02) 9317 9911 fax: (39 02) 9317 9913 europe north phone: (44 1344) 486 444 fax: (44 1344) 486 555 europe south phone: (33 1) 41 44 36 50 fax: (33 1) 41 44 36 90 middle east headquarters conexant systems commercial (israel) ltd. p. o. box 12660 herzlia 46733, israel phone: ( 972 9) 952 4064 fax: (972 9) 951 3924 japan headquarters conexant systems japan co., ltd. shimomoto building 1-46-3 hatsudai, shibuya-ku, tokyo 151-0061 japan phone: (81 3) 5371-1567 fax: (81 3) 5371-1501 taiwan headquarters conexant systems, taiwan co., ltd. room 2808 international trade building 333 keelung road, section 1 taipei 110, taiwan, roc phone: ( 886 2) 2720 0282 fax: (886 2) 2757 6760 so990810(v1.3) |
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